AMD/Xilinx Design Services
Today, FPGA design is far more than implementing glue logic. With the complexity of today's FPGA devices it becomes cost-efficient to implement programmable system-on-chip solutions with multiple processor cores, heterogeneous accelerators and peripheral blocks interfacing with multi-gigabit transceivers, for example. Therefore, a successful FPGA project demands a holistic approach and dependable relationships with 3rd party IP core vendors and close collaboration with the FPGA vendors.
As a Premier Partner in the AMD/Xilinx Alliance many of our FPGA design engineers have certified their expertise in
- Xilinx PetaLinux on Micro-Blaze, Zynq, Zynq Ultrascale+ MPSoC
- Xilinx Zynq-7000 All-Programmable SoC
- Xilinx Zynq UltraScale+ MPSoC
- Xilinx GTP/GTX/GTH/GTY transceiver parameterization and instantiation
- Xilinx ISE design flow with XPS and ChipScope Design Analysis
- Xilinx Vivado design flow following Xilinx UltraFast Design Methodology
- Xilinx Vivado High-Level-Synthesis using C/C++/SystemC design entry
- Xilinx Vitis design
- Xilinx SDx toolchain for SDAccel, SDNet, SDSOC
AMD/Xilinx trusts our team with maintenance and service of the XPS USB 2.0 EHCI host controller soft IP core, the Xilinx XAUI and RXAUI IP Cores, and with PetaLinux (2014.2 up to current) development support.
MLE's equipment includes licenses for Xilinx Vivado, Xilinx Vitis and Vivado HLS (2013.3 up to current), legacy tool chain Xilinx ISE (version 10.1 up to 14.7).
MLE also uses a variety of current and legacy development kits from Xilinx direct such as, for example: ML403, ML507, ML605, SP605, KC105, VC707, VC709, ZC702, ZC706, ZCU102, ZCU106, or ZCU111 from the Xilinx ecosystem, such as, for example: Avnet miniITX 7045, Avnet miniITX 7100, Enclustra ZX3, ProFPGA.