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Past Projects

  • TCP/UDP/IP Full Acceleration for Medical Imaging

Integrate and enhance Network Protocol Accelerator Platform (NPAP) for up to 50 Gbps line rates; aggressive resource optimization using asymmetric packet buffer schemes; enhance for application-specific Quality-of-Service (QoS) behavior.

  • Many-Sensor Pre-Processing System Using AMD/Xilinx KRIA System-on-Module (SoM)

Design system-level architecture; PCB schematics design for custom baseboard using Altium, collaborate via Altium Live; pin planning for HDMI-to-LVDS display output.

  • PCIe Card Implementation Using Microchip PolarFire FPGA

Pro-active obsolescence management and hardware re-design of PCI card; support PCB design team with FPGA pin planning for industrial interfaces; migrate legacy FPGA subsystems from Xilinx Spartan 6 to Microchip PolarFire; PCIe subsystem integration which ensure software-level compatibility with legacy PCI software and device drivers; hardware bringup and test.

  • Xilinx XAUI IP Core Long-Term Support

Receive and augment Xilinx XAUI and RXAUI IP core; implement RTL simulation and verification environment using Questa / ModelSim from Mentor Graphics / Siemens EDA; migrate from legacy FPGA devices to Xilinx UltraScale and Xilinx UltraScale+ multi-gigabit transceivers.

  • 4k Video Image Processing in Xilinx UltraScale+ MPSoC

Implemented for Xilinx Zynq Ultrascale+ MPSoC ZU7EV; integrated dual-channel HDMI 4k DCI inputs and outputs; integrated dual-channel SDI-12G inputs and outputs; enhance Xilinx video processing chain and management software; instantiate PCIe Gen3 hard IP core for 8 GT/s and x8 lanes, configure for PCIe peer-to-peer with NVidia RTX4000 GPU for low-latency image co-processing and alpha blending; support PCB design team with pin planning and hardware bringup testing.

  • SmartNIC System Design and Implementation

PCB schematics design and layout for Stratix 10 GX HHHL PCIe card; integrate PCIe Gen3 8GT/s x8 lanes; 4x SFP+ ports for 10 Gigabit Ethernet; instantiate FPGA NIC framework for In-Network Processing, extend with custom traffic shaping and Layer-2 and Layer-3 protocol encapsulation; hardware bringup and test; Linux PCIe device driver implementation and integration & test against customer Linux user space application.

  • TCP/UDP/IP Full Accelerator Code Migration to Microchip Polarfire

Migrate Fraunhofer TCP/UDP/IP VHDL code to PolarFire and adjust VHDL code base for non-volatile Flash-based structures; integrate with 5 Gigabit Ethernet and 10 Gigebit Ethernet subsystem; test on MPF300 Development Kit.

  • Application-specific FPGA to FPGA communication protocol

Implemented for Xilinx Zynq Ultrascale+ MPSoC and Xilinx 7-Series devices; use of LVDS pins with 8b10b coding and scrambling for a data rate of 100 Mb/s; use of IDELAY primitives or fast clocked Flip Flops for data eye analysis and sampling point adjustment (training); Flow control support for packetized upper layer communication protocol.

  • FPGA Code Optimization for Intel Agilex HyperFlex

IP Core throughput optimization using Agilex HyperFlex architecture; augment VHDL RTL code with additional pipelining stages, timing closure; close collaboration with experts from Intel PSG.

  • 4k Video Processing in FPGA with HDMI 2.0

Support a semi-custom / chip-down PCB design based on FPGA System-on-Module from Trenz Electronics with HMDI Input and Output, hardware bring-up and testing, integrate and test HDMI 1.4/2.0 Rx and Tx subsystem (Xilinx PG236 v3.1 and PG235 v3.1) for 4k video processing, integrate Xilinx PetaLinux-based processing system for management and control.

  • 40 Gbps SD-WAN Accelerator / SmartNIC

Offload SD-WAN OpenVSwitch from x86_64 Linux server to SoC-FPGA, implement 4x 10 GigE SmartNIC subsystem using data-in-motion network processing, FPGA subsystem development in HDL and in C/C++ using High-Level Synthesis (HLS), traffic shaping and Linux netdev interfacing, plan for aggressive cost-down options.

  • Long-Range Tunneling of MIPI camera streams over TCP/IP over 1G / 10G Ethernet

Design and test of a working proof-of-concept implementation for MIPI D-PHY, MIPI CSI-2, I2C camera sensor processing in a networked, distributed processing system; use of I2C clock stretch to compensate for network delay and to allow for efficient byte wise network transport; integrated and tested with MIPI D-PHY Rx/Tx IP Core (Xilinx PG202 v4.1), MIPI CSI-2 Rx IP Core (Xilinx PG232 v4.0), MIPI CSI-2 Tx IP Core (Xilinx PG260 v2.0), Fraunhofer HHI TCP/IP Full Accelerator (MLE NPAP v1.4) on Xilinx Zynq Ultrascale+ MPSoC; enhanced with multi-cast capabilities to transport MIPI CSI-2 camera video stream to multiple video receiver SoCs.

  • Implementation of Xilinx IDELAY based fast 3 GS/s ADC parallel LVDS interface

Implemented for Xilinx Virtex 7; use of multiple LVDS pairs with 750 Mb/s each; use of IDELAY primitives for data eye analysis and sampling point adjustment (initial training and tracking/adjustment over wide temperature range).

  • 25G TCP/IP Network Protocol Acceleration for Xilinx UltraScale+ RFSoC

Ported Fraunhofer HHI TCP/IP and UDP Full Accelerator to the Xilinx RFSoC ZCU111 platform, integrated with 25G PCS/PMA subsystem (Xilinx PG210 v2.5), verify and test 25 Gbps linerate performance, latency and interoperability against Mellanox Technologies ConnectX-4 Lx EN.

  • Remote FPGA Lab Access for Work-from-Home (WfH)

To continuously support various customers in the COVID pandemic situation, MLE enabled customers to remotely access and operate FPGA lab setups interactively. Integrated Open Source GitLab, Labgrid, Guacamole.

  • Low Latency REST API server

A Low latency REST API server has been implemented on the PS in an Zynq7000 and Petalinux.

  • Time-Sensitive Networking (TSN) in FPGA

Integrate and benchmark Fraunhofer IPMS TSN-SE IP Core in proFPGA ASIC emulation environment, diagnose and verify Precision Time Protocol PTPv2 / IEEE 802.1AS using Open Source Wireshark capture and PPS analysis on Oscilloscopes, diagnose and verify IEEE 802.1Qav Credit Based Shaper and IEEE 802.1Qbv Scheduled Traffic, extended resource and management API running on embedded soft CPU.

  • Speed-up FPGA Boot Times for Automotive

Using SelectMap (Xilinx XAPP583) implement faster FPGA config & boot for Artix-200, Lattice MachXO2 CPLD and QSPI Flash memory interfaces.

  • SATA Storage Subsystem for SSD Array

Integrate 3rd party ASICS World-Services SATA IP Core into Xilinx Zynq-7100 for automotive datalogging onto SSD Array, implement and test RAID-style striping architecture to achieve high SSD read/write performance.

  • UDP Acceleration for Automotive Datalogger

Integrate 3rd party Fraunhofer HHI UDP/IP stack, implement custom data download and control protocol in Xilinx Zynq-7100.

  • TCP/IP Acceleration using Xilinx Virtex-6 and Virtex-7

Integrate 3rd party Fraunhofer HHI TCP/IP stack, clock domain partitioning to make timing closure for very high device utilization.

  • Single-chip solutions for a digital Pseudo Noise Radar using Xilinx Zynq UltraScale+ RFSoC

Architecture exploration to reach 30 FPS performance goal. FPGA development using HDL and High-Level Synthesis (Vivado HLS) for buffering and data-in-motion reorg using external PL-attached DDR4 RAM, FFTs, correlation, ARM A53 software under Linux for data IO and visualization.

  • NVMe stream recording using FPGA and SSD

Integrate Xilinx plus in-house plus open-source IP cores into Virtex-7 based Micro-TCA off-the-shelf hardware. Evaluation SSD vendors for extended temperature ranges and NVH. Diagnose and test NVMe write performance for lossless recording.

  • OS integration and hardening in an multi FPGA NUMA architecture on Xilinx Ultrascale+ MPSoC

Integrate OS into multi FPGA architecture; USB and PCIe error mitigations on OS level as well as Hardware (FPGA) level; System turn-on and bringup and analysis to specification.

  • Time-Synchronized Audio Transmission based on Xilinx Zynq Ultrascale+ MPSoC

Reception of IRIG-B12x, IRIG-B00x and HaveQuick time information; Transmission of sets of audio samples at software defined points in time; Augmentation of received audio samples with timestamp information; Xilinx PetaLinux drivers and integration.

  • ADAS communication infrastructure based on Xilinx Zynq UltraScale+ MPSoC

PCB-level design support, bring-up and interface testing of a Zynq UlraScale+ MPSoC based ADAS communication infrastructure. Architecture design and implementation of PCIe and NTB based communication infrastructure and data stream distribution from sensors to compute modules.

  • RFSoC with GNU Radio

Design and implement a proccessing chain to access the high speed DAC and ADC of the RFSoC. This chain can be accessed by GNURadio, a open source software defined radio implementation. To acces the processing chain, MLE implemented a configureable sink and source block for GNURadio.

  • Datacenter Storage Node based on Xilinx Zynq Ultrascale+ MPSoC

PS- and PL-attached NVMe connectivity using Xilinx IP cores and Xilinx PetaLinux; integration and test of 10G/25G Ethernet and Network Protocol Acceleration; integration and test of Xilinx NVMe-over-fabric technology.

  • Xilinx PetaLinux Designflow for Xilinx Zynq Ultrascale+ MPSoC

Educate and support customer with software development and designflow aspects for ZU+ MPSoC; set up Xilinx PetaLinux build environment under Linux, integrate into agile development process.

  • Cloud migration of an FPGA-accelerated Deep-Learning application to Amazon AWS EC2 F1 instance

Migrate existing embedded system for FPGA-accelerated Deep-Learning to Amazon AWS EC2 F1 FPGA instance; adopt FPGA designflow to AWS based FPGA designflow; port embedded Linux with Jupyter Python subsystem to AWS EC2 F1 Linux AMI; integrate and test FPGA design and port to AWS AFI; setup and register in Amazon AWS marketplace.

  • Automotive multi-camera vision system based on Xilinx Zynq and Zynq UltraScale+ MPSoC

System-level software architecture design; FPGA platform development using multi-input, multi-buffer Video-DMA and HDMI monitor output; porting Lukas-Canade Optical Flow IP core; C++ software acceleration using Xilinx Vivado HLS and Xilinx SDx toolchain.

  • Automotive heterogeneous compute platform for Radar / Lidar image processing on Xilinx Zynq UltraScale+ MPSoC

Configuration and testing of base Xilinx PetaLinux system (FSBL, kernel, DTS); BroadR-Reach PHY Linux driver development; development of shared memory buffers and IPI communication between Linux on ARM Cortex A53 and AutoSAR/bare metal on ARM Cortex R5; system clocking architecture and design "hardening" via XMPU, XPPU.

  • Heterogeneous Data Processing for a 4-channel, 5.6 Gbps Wind-Lidar system

High-speed analog ADC / DAC interfacing via JESD204B; FPGA based proprocessing and decimation filtering in Xilinx Virtex-7 690T FPGA; FFT and cross-correlation filter in TI TMS320C6678 DSP; Windows and Linux based GUI design on x86 CPU module in micro-TCA form-factor.

  • PCI-Express Gen3 Test & Measurement System in Xilinx Virtex-7 690T FPGA

Diagnostics for PCIe low-power states; acceleration of read/write for PCIe address space modules; design of integrated Bit-Error-Rate Tests (iBERT); PCIe upstream and downstream switch modules; diagnostics for PCIe multi-lane de-skew; PCIe specification conformity analysis.

  • Tunneling of PCI-Express Transaction-Layer-Packets (TLP) with TCP/IP over 10G Ethernet

Design and test of a working proof-of-concept implementation on Xilinx Zynq-7000 (ZC706); integration of 3rd-party full accelerators; latency analysis at PCIe clock accuracy using Tracer packets and Xilinx Integrated Logic Analyzer (ILA).

  • CPLD development under SIL-2

Implementation of fully synchronous design in VHDL, interface and data processing with 3D optical sensor, set-up of verification and validation environment, implementation in Lattice MachXO3 CPLD, close collaboration with customer and FPGA vendor to meet TÜV certification for Safety-Integrity Level 2 (SIL-2).

  • IO-Link Device Stack implementation on micro-controller

Requirements analysis based on IO-Link specification Version 1.1.1, implementation of a design and validation environment in SystemC, 8-bit micro-controller programming in ANSI C/C++ for Atmel ATmega168, porting and 32-bit optimization for ST STM32 micro-controller.

  • Multi-Port SATA-6G Host-Controller

System-on-Chip architecture design, on-chip connectivity of 3rd party SATA Host Controller and DMA soft IP core with FPGA-based PCIe hard IP end-point, implementation in Altera Stratix-IV 230 and Xilinx Virtex-7 485, SATA and PCIe device driver development for Linux.

  • PCI Express Gen3 x8 Bridge Architecture

Integration of 3rd party PCIe Gen3 soft IP core for PCIe Up- and Down-Switch-Ports, close collaboration with IP core vendors and FPGA vendor, PCIe BAR architecture design, interfacing with COM Express Intel CPU module running Ubuntu Linux with Long-Term Support, Linux device driver development.

  • Wireless HDMI Adapter for SDI-3G

System-, FPGA- and PCB-level design review, enhancement of streaming video system to support 1080p, 1080i, 720p, 480p and 576i video formats, implementation of anti-jitter solution in HDL, FPGA design using Altera Video IP Suite for Cyclone IV E device, development of system-level test environment based on COTS modules, close collaboration with FPGA distributor.

  • Protocol Accelerators for AHCI and NVM-Express

FPGA implementation in Xilinx Virtex-7 690, Linux device driver and application software development under Ubuntu Linux, connectivity for Solid-State-Disks (SSD) running Advanced Host-Controller Interface (AHCI) and Non-Volatile Memory Express (NVMe) protocols.

  • Multi-Port SAS-12G Initiator

Integration of multiple instances of 3rd-party SAS Initiator and DMA soft IP cores in existing Xilinx Virtex-7 FPGA design, close collaboration with 3rd-party IP core vendor, on-chip and off-chip analysis for high-speed serial transceiver connectivity, close collaboration with FPGA vendor for migration from Xilinx GTX to Xilinx GTH transceiver technology.

  • PCI Express Gen2 x2 Device

Integration of customer-provided functionality with FPGA hard IP end-point, BAR mapping for Intel Qseven-based embedded system, device driver and PCIe test development for Linux, seamless migration from Altera Arria-V GX starter kit to customer target hardware.

  • 10 GigEthernet Network Protocol Accelerator

Modularization of 3rd party IP core in VHDL, adaptation to IP core centric design flow in Xilinx Vivado 2014.4, integration with Xilinx Zynq All-Programmable SOC via AXI4 interfaces, PetaLinux device driver deleopment, implementation of test environment based on Xilinx ZC706 Development Kit.

  • OpenAMP for Xilinx Zynq

Implementation of Non-Uniform Memory Access (NUMA) architecture, integration of Mentor OpenAMP Asynchronous Multi-Processing with interfaces between real-time RTOS on first core and PetaLinux on second CPU core, integration of Diskrete Fourier-Transformation (DFT) block in Zynq Programmable Logic (PL) with ARM A9-MP multi-core CPU via AXI-4 on-chip connect.

  • Video-for-Linux (V4L2)

Integration of 3rd party PCIe and Video-DMA IP cores in Xilinx Zynq-7000 All-Programmable SOC, PCIe connectivity to Intel CPU under Linux, Linux device driver and application software development for frame-buffer and frame-grabber device functionality.

  • USB 2.0 Host Controller

Design analysis and functionality enhancements for MicroBlaze and PetaLinux based embedded system for USB-attached storage application, close collaboration between customer and FPGA vendor during migration to TÜV-certified FPGA tool chain and design flow.


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