Request Information for IP-Cores and Licensable Subsystem Stacks

XPS USB 2.0 EHCI Host Controller

As of October 2011, Xilinx handed over to MLE sales and support for the Xilinx XPS USB 2.0 EHCI Host Controller. Available in Revision 2.00a, this IP Core allows users to connect FPGAs to full-speed and high-speed USB devices for human-machine interface applications, cameras and storage. The current release supports Spartan-3, Spartan-6 or Virtex-4, Virtex-5, Virtex-6 FPGAs in a Big-Endian PLB-based architecture. A Little-Endian AXI4-based architecture for 7-series FPGAs will be available soon.



Extend FPGA-based Embedded Systems with USB 2.0 connectivity to add Off-the-shelf components for:

  • Thumbdrive storage
  • HDD and SSD storage
  • Human Interface Devices (HID)
  • Bluetooth
  • WiFi 802.11abgn
  • etc


Core Benefits

  • Reduce PCB footprint and BoM costs with this integrated FPGA solution.
  • Reduce development cost, time and risks with this integrated, pre-validated system stack.
  • Counter parts obsolescence.
  • Supported by Linux and PetaLinux.



MLE provides a three-phase product integration roadmap for customers:

Product Name Deliverables Pricing

Trial Version

Integrated and delivered with Xilinx ISE. Fully functional with timeout after approx. 4 hours.

free of charge

Production License

Single-Project or Multi-Project Use License; shipped as encrypted RTL code plus Xilinx ISE synthesis license key.

starting at $20,000.-


Support from Certified Xilinx engineers at MLE available on a T&M basis. Please inquire!

Source code

RTL Source Code for inspection purposes available under NDA. Please inquire!



The XPS USB 2.0 EHCI host controller (as IP core or reference design) is available for the following FPGA families:

Products Availability Matrix

Datasheets and Documentation

Download the original Xilinx datasheet.

For more information about functionality and integration, please refer to our XPS USB Host Controller Developer's Guide.

Xilinx has published additional information on their Xilinx Wiki: