MLE NPAC-40G Now Runs CORUNDUM System Stack

MLE has ported and tested a full system stack based on CORUNDUM for NPAC-KETCH, CORUNDUM is a vendor-neutral open source high-performance FPGA-based SmartNIC development platform. NPAC-KETCH is a FHHL PCIe card featuring 4 SFP+ ports for 10 Gigabit Ethernet, PCIe 3.1 8 GT/sec x8 lanes, and In-Network Processing using Intel's Stratix 10 GX 400 FPGA.


MLE NPAC-40G - A Cost-Efficient PCIe SmartNIC Solution

MLE has partnered with Fraunhofer HHI and Elemaster Germany to provide the industry-proven TCP/UDP/IP Network Protocol Accelerator Platform (NPAP) in form of NPAC-40G, a PCIe Network Protocol Accelerator Card. NPAC-40G implements reliable high-bandwidth low-latency TCP/UDP/IP transport plus Linux PCIe stream drivers and, optionally, can run customizable In-Network Processing using the Intel's Stratix 10 GX 400 FPGA.


MLE Releases NPAP TCP/UDP/IP Stack Version 1.8.0

MLE has released Version 1.8.0 of NPAP, the TCP/UDP/IP Full Accelerator from Fraunhofer HHI. Changes include fixes for UDP, padding for Ethernet frames smaller than 60 Bytes and an increase of the maximum number of TCP Session instances. Please refer to the updated datasheet MLE TB20220408 for more information.


CORUNDUM Project Releases AMD/Xilinx Zynq MPSoC Support

CORUNDUM, the open source In-Network Compute Platform hosted on Github now supports the integrated ARM A53 Processing System of AMD/Xilinx Zynq UltraScale+ MPSoC FPGA. Based on key contributions from MLE this work allows implementing complete Linux subsystems running within the SmartNIC, separate and independent from the underlying host operating system. Work was tested using the Sidewinder-100 card from Fidus Systems, a fellow AMD/Xilinx Alliance member.


MLE Integrates CORUNDUM MQNIC Support into DPDK

MLE has integrated support for the CORUNDUM project's MQNIC into the open source Data Plane Development Kit. MQNIC is the open source network interface card within CORUNDUM, the open source FPGA-based In-Network Compute Platform. DPDK now has support for a single interface and a single port per interface of MQNIC. MLE work was tested with a 10G version of MQNIC build for the Fidus Sidewinder-100 board which features an AMD/Xilinx Zynq UltraScale+ MPSoC ZU19EG.


MLE Presents at SmartNICsSummit 2022

At SmartNICsSummit 2022, MLE will present "Platform Choices for FPGA-Based In-Network Compute Acceleration" which is joint work with the Corundum project and Fraunhofer HHI. SmartNICs and Function Accelerator Cards address performance issues in Software-Defined Networking (SDN) as network port speeds increasingly outstrip CPU performance. SmartNICsSummit will be held April 26-28, 2022, in San Jose, CA.


MLE NVMe Streamer Passes PCIe 4.0 Testing

MLE has successfully tested NVMe Streamer a so-called Full Accelerator NVMe host subsystem for PCIe 4.0. Test setup was the Xilinx ZCU216 Development Kit featuring Zynq UltraScale+ RFSoC Gen3, and the new FPGA Drive FMC Gen4 from partner Opsero. The combined solution doubles bandwidth for modern PCIe Gen4 x4 M.2 NVMe SSD.


Fraunhofer IPMS and MLE Present at Automotive Ethernet Congress, June 1-2, 2022

At the Automotive Ethernet Congress 2022, on June 2nd we present "Zone-Based Automotive Backbone" a.k.a. Auto/TSN which is joint work between MLE and Fraunhofer IPMS on how to combine TSN Ethernet, TCP/IP as an ultra-reliable deterministic low-latency transport for tunneling PCIe and other protocols for long-reach. The joint presentation also features a lab car demo in which tunneling effects on bandwidth and latency within the network will be explained.


NPAP RTL Simulation Demonstrates Low-Latency TCP/IP

MLE has complemented NPAP, the TCP/UDP/IP Full Accelerator from Fraunhofer HHI, with an RTL Simulation environment for Xilinx Vivado ISim and for the Questa Advanced Simulator from Siemens EDA. This simulation environment is available free-of-charge to all licensees of NPAP with an active maintenance subscription. For more information please read the MLE Technical Brief TB20220305 titled "Latency Measurement of 10G/25G/50G/100G TCP-Cores Using RTL Simulation".


MLE & Intel PSG Optimize NPAP for Intel HyperFlex Architecture

As the outcome of joint engineering collaboration between Intel PSG and MLE Germany, an new version of NPAP, the TCP/UDP/IP Full Accelerator from Fraunhofer HHI was released by MLE. This release incorporates many code optimizations for utilizing the Intel HyperFlex technology. Intel HyperFlex FPGA Architecture addresses increased bandwidth demands via improved FPGA logic clocking. For a typical NPAP setup clock speed was improved by more than 1.5x to currently over 500 MHz. Because of NPAP's unique 128-bit wide datapath architecture, this enables more than 60 Gbps line rates. NPAP-100G for Intel Hyperflex is made available by MLE as a licensable subsystem stack or as a Function Accelerator Card based on Stratix 10GX devices.