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      • Home
      • Network Acceleration

      # Network Acceleration

      Deterministic Networking with TSN-10/25/50/100G

      Deterministic Networking with TSN-10/25/50/100G

      Dec 4, 20204 years ago

      MLE presents “Deterministic Networking with TCP-TSN-Cores for 10/25/50/100 Gigabit Ethernet” in Technical Brief MLE-TB20201203.

      MLE Releases Update V1.4.9 for 10/25/40/50G TCP/IP Stack

      MLE Releases Update V1.4.9 for 10/25/40/50G TCP/IP Stack

      May 19, 20205 years ago

      Missing Link Electronics (MLE) has released update V1.4.9 for the network acceleration technology from German Fraunhofer Heinrich-Hertz-Institute. Changes include various fixes for corner cases and to enhance support for the…

      MLE Releases 10/25 Gig Ethernet NPAP for Intel Stratix 10 FPGAs

      MLE Releases 10/25 Gig Ethernet NPAP for Intel Stratix 10 FPGAs

      Feb 9, 20205 years ago

      With great support from the Intel PSG Team Europe, MLE has ported the 10/25 Gigabit Ethernet Network Protocol Acceleration Platform (NPAP) based on the TCP/UDP/IP Network Protocol Accelerator from Fraunhofer…

      Network Protocol Acceleration with CAPI SNAP

      Network Protocol Acceleration with CAPI SNAP

      Oct 4, 20186 years ago

      Presentation at IBM OpenPOWER Summit Europe 2018 in Amsterdam, NL. Addressing Network Protocol Acceleration for IBM OpenPOWER Power8 and Power9 with the Coherent Accelerator Processor Interface (CAPI) Storage, Networking and…

      Fraunhofer HHI and MLE to Collaborate on 25/50G Ethernet MAC

      Fraunhofer HHI and MLE to Collaborate on 25/50G Ethernet MAC

      Sep 28, 20177 years ago

      German Fraunhofer Heinrich-Hertz-Institute (HHI) and MLE collaborate to enhance Fraunhofer HHI's Low-Latency Ethernet MAC and TCP/IP Stack to support Xilinx UltraScale+ GTY Transceiver Technology for 25/50 Gig Ethernet.  

      FPGA-Based Hardware Accelerators for 10/40 GigE TCP/IP and Other Protocols

      FPGA-Based Hardware Accelerators for 10/40 GigE TCP/IP and Other Protocols

      Dec 14, 20159 years ago

      Presentation at the DESY MTCA Workshop for Industry and Research in Hamburg Hardware-acceleration of networking protocol stacks, enabled to be optimized for specific applications and underlying network protocols, going beyond…

      High-Level Synthesis for FPGA Implementation of Network Protocols

      High-Level Synthesis for FPGA Implementation of Network Protocols

      Feb 24, 201510 years ago

      Presentation at the Embedded World Conference 2015 Combining network protocol acceleration technology from Fraunhofer HHI with Vivado HLS for programming Xilinx Zynq All Programmable SoC. (download slides)  

      Low-Latency Networking for Systems-of-Systems

      Low-Latency Networking for Systems-of-Systems

      Mar 15, 201411 years ago

      Presentation at Embedded World Conference 2014 How hardware acceleration helps reducing latency and increasing bandwith. (download slides)