Technical Publications
MLE has been invited to numerous international seminars and webinars to share our experience in FPGA development using advanced PCI Express, TCP/UDP/IP stacks, and low-latency IP-core technologies for network and storage acceleration. Here we share the full technical articles and slides of the up-to-date presentations.
Programming Reconfigurable Devices
Programming Reconfigurable Devices via FPGA Regions & Device Tree Overlays A technical presentation given by Dipl.-Ing. Ulrich Langenbach and M.Sc. Stefan Wiehler at FOSDEM 2017. A User View Benchmark on…
Heterogeneous Architectures for Implementation of High-capacity Hyper-converged Storage Devices
Presentation at the SNIA Storage Developers Conference 2016 in Santa Clara, CA. A Xilinx Zynq Ultrascale+ based hybrid memory system mixing NVMe drives and DRAM to deliver multi-terabyte object store…
PCI Express over IP, Accelerated – A Low Latency Fabric for System-of-Systems
Presentation at Session 18/II of the Embedded World Conference 2016 in Nuremberg FPGA-based full accelerators enable reliable tunneling of PCI Express of existing LAN. This approach is transparent to the…
Designing FPGA-Accelerators for Linux Software Using High-Level Synthesis
Presentation at Session 18/II of the Embedded World Conference 2016 in Nuremberg High-Level Synthesis facilitates a new, efficient design methodology to accelerate (legacy) software with FPGA-based hardware accelerators. (download slides)…
FPGA-Based Hardware Accelerators for 10/40 GigE TCP/IP and Other Protocols
Presentation at the DESY MTCA Workshop for Industry and Research in Hamburg Hardware-acceleration of networking protocol stacks, enabled to be optimized for specific applications and underlying network protocols, going beyond…
Langzeitverfügbarkeit mit All-Programmable SoCs
Presentation at the IHK Erfa-Kreis Embedded Systems (German Chamber of Commerce) in Augsburg Presenting benefits of FPGA technology for controlling bill of materials in industrial use cases. (download slides)
Testkonzepte für FPGA/ASIC-Entwicklung
Presentation at the Test-Engineering-Day in Neu-Ulm 2015 Agile design and testing/verification of FPGA and ASIC hardware components. (download slides)
High-Level Synthesis for FPGA Implementation of Network Protocols
Presentation at the Embedded World Conference 2015 Combining network protocol acceleration technology from Fraunhofer HHI with Vivado HLS for programming Xilinx Zynq All Programmable SoC. (download slides)
Beschleunigen von Algorithmen mit Vivado HLS auf dem Xilinx Zynq
Presentation at the Konferenz für ARM-Systementwicklung 2014 High-Level-Synthesis Design for Xilinx Zynq Accelerators with Vivado HLS (in German). (download slides)
Low-Latency Solutions for Storage-Hungry Embedded Applications
Presentation at Flash Memory Summit 2014 A case for low-latency Ethernet connectivity for Solid-State Disks (SSD). (download slides)