Architecture and Performance of Integrated High-speed and Versatile Embedded Networking

These days high-performance embedded systems operate highly interconnected. Within these networks the systems often transport data at high bandwidth or low-latency. While the system needs to serve the network performance needs, additional control tasks are to be performed. For the latter task usually a processing system runs a Linux or another real-time embedded operating system. Then the former, high-performance network data cannot be fully handled by the embedded processing system. Thus a high-speed and Versatile Embedded Networking is needed.

To overcome this situation, a network stack implemented in hardware, e.g. in an FPGA, can offload the processing subsystem. To simplify the system design and reduce cost, the number of physical networking interfaces can be reduced to one. This, on the other hand, requires an architecture that shares a single high-speed network interface across the processing system and the hardware network stack. Usually, embedded systems in addition require highly accurate time synchronization, usually provided via PTPv2.

The presentation shares the architecture options and results based on an implementation for a high-speed streaming data interface, both a source and a sink that shares a physical network interface with a open source network interface card implementation connected to a processing system. This NIC is operated by a Linux driver and allows for PTPv2 based time synchronization via a Linux daemon. The whole system is implemented into an AMD MPSoC.