PCI Express over IP, Accelerated - A Low Latency Fabric for System-of-Systems

Presentation at Session 18/II of the Embedded World Conference 2016 in Nuremberg

FPGA-based full accelerators enable reliable tunneling of PCI Express of existing LAN. This approach is transparent to the CPU Root Complex and Operating System and can be scaled to match 1/10/25/40 GigE line rates.

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Designing FPGA-Accelerators for Linux Software Using High-Level Synthesis

Presentation at Session 18/II of the Embedded World Conference 2016 in Nuremberg

High-Level Synthesis facilitates a new, efficient design methodology to accelerate (legacy) software with FPGA-based hardware accelerators.

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FPGA-Based Hardware Accelerators for 10/40 GigE TCP/IP and Other Protocols

Presentation at the DESY MTCA Workshop for Industry and Research in Hamburg

Hardware-acceleration of networking protocol stacks, enabled to be optimized for specific applications and underlying network protocols, going beyond a state-of-the-art TCP/IP Offload Engine (TOE) and reaching userspace latencies faster than 1 microsecond.

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Langzeitverfügbarkeit mit All-Programmable SoCs

Presentation at the IHK Erfa-Kreis Embedded Systems (German Chamber of Commerce) in Augsburg

Presenting benefits of FPGA technology for controlling bill of materials in industrial use cases.

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Testkonzepte für FPGA/ASIC-Entwicklung

Presentation at the Test-Engineering-Day in Neu-Ulm 2015

Agile design and testing/verification of FPGA and ASIC hardware components.

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High-Level Synthesis for FPGA Implementation of Network Protocols

Presentation at the Embedded World Conference 2015

Combining network protocol acceleration technology from Fraunhofer HHI with Vivado HLS for programming Xilinx Zynq All Programmable SoC.

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Beschleunigen von Algorithmen mit Vivado HLS auf dem Xilinx Zynq

Presentation at the Konferenz für ARM-Systementwicklung 2014

High-Level-Synthesis Design for Xilinx Zynq Accelerators with Vivado HLS (in German).

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Low-Latency Solutions for Storage-Hungry Embedded Applications

Presentation at Flash Memory Summit 2014

A case for low-latency Ethernet connectivity for Solid-State Disks (SSD).

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A synthesis strategy for nonlinear model predictive controller on FPGA

2014 UKACC International Conference on Control

An implementation strategy of nonlinear model predictive controller for FPGA systems using high-level synthesis of a real-time MPC algorithm by means of the Xilinx Vivado HLS tool is discussed.

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Analog Solutions for Smart Products

Presentation at Embedded Conference 2014

How FPGAs support analog input without a dedicated ADC.

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