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Platform Choices for FPGA-Based In-Network Compute Acceleration

Presentation at SmartNICsSummit 2022, April 26-28, 2022

FPGA-based SmartNICs can provide significant benefits by offloading network data processing off of CPU cores, data-in-motion processing, effectively enabling In-Network Compute. However, FPGA programming requires special skill sets to render predictable quality results. Open and open-source platforms such as NPAP or CORUNDUM or AMD OpenNIC or Intel IOFS can reduce the costs and risks when implementing FPGA-based SmartNICs. This is a joint presentation between MLE and UC San Diego, Dr. Alex Forencich.

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CORUNDUM - From a NIC to a Platform for In-Network Compute

Presentation at FOSDEM'22, February 5-6, 2022

This joint presentation between Alex Forencich, UC San Diego, and Ulrich Langenbach, MLE, provides an introduction to the corundum project, implementing a 100 GbE NIC based on Commercial-off-the-shelf (COTS) FPGA cards, e.g. Xilinx Alveo. The project consists of all necessary RTL components, e.g. PCIe DMA engine, NIC datapath, MAC, PHY and integration of vendor specific IP cores, such as transceivers and PCIe hard-IP cores. In combination with the provided driver and debugging utility the ready-to-experiment state just requires a supported FPGA card + compiler to kick-off playing with the project.

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Zone-Based Automotive Backbones Tunneling PCIe

Presentation at PCI-SIG Virtual Developers Conference 2021, May 25-26

The need for more safe and eco-friendly vehicles drives automotive connectivity towards so-called Zone-Based Architectures. Inside those so-called Zone Gateways PCIe technology provides the connectivity between multiple System-on-Chip (SoC), CPUs, GPUs, and FPGAs for scalable performance. Within the automotive network, multiple Zone Gateways connect with each other via the emerging IEEE standards “Time Sensitive Networking” (TSN).
Today, Fraunhofer and MLE can provide a working proof-of-concept in form of a digital circuit & system stack which encapsulates and decapsulates PCIe packets (and other protocols) over real-time automotive TSN Ethernet and which scales up to 100 Gbps.

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Presentation at 4th Workshop "Programmable Processing for the Autonomous / Connected Vehicle", Sept. 24, 2020 at TH Ulm, Germany

ADAS and Autonomous Driving push the migration towards Zone-based architectures, which again push for more bandwidth and real-time capabilities in the Automotive Network. Based on open IEEE standards and a unique combination of technology from Fraunhofer Heinrich-Hertz-Institute, from Fraunhofer Institute for Photonic Microsystems and from Missing Link Electronics, PCI Express, and other protocols, can be transported in real-time at datarates of 10 Gbps, and more.

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Security / Trusted Execution Environment and Functional Safety with Zync Ultrascale+ MPSoC / RFSoC

Presentation at the Workshop Programmable Processing for the Autonomous / Connected Vehicle 2019 in Neu-Ulm

The security of Embedded Systems has become a key concern, especially when hacked or tampered systems create safety issues and can harm people. In order to make an embedded system secure, CPU vendors like ARM offer the TrustZone technology. On top of this ARM TrustZone technology sits Open Portable (OP)-Trusted Execution Environment (TEE), an open source implementation of the TEE.

OP-TEE is a small secure operating system which, after authentication and description, gets loaded in an secured area in the memory. A Rich OS (e.g. Xilinx PetaLinux) driver can request, via a Secure Monitor Call, the execution of a trusted application. MLE took the effort to port OP-TEE to Xilinx Zync UltraScale+ MPSoC Platform, including device specific optimizations.

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Sensor Fusion and Data-in-Motion Processing for Autonomous Vehicles

Presentation at PCI-SIG Developers Conference 2019 in Santa Clara, CA

Using PCIe Non-Transparent Bridging to connect multiple CPUs/GPUs/SoCs/FPGAs within an automotive ECU. This heterogeneous architecture meets tight Size-Weight-and-Power requirements and combines processing flexibility with sufficient bandwidth at deterministic low latency to run algorithms from classical image processing over Deep-Learning to real-time control algorithms.

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Network Protocol Acceleration with CAPI SNAP

Presentation at IBM OpenPOWER Summit Europe 2018 in Amsterdam, NL.

Addressing Network Protocol Acceleration for IBM OpenPOWER Power8 and Power9 with the Coherent Accelerator Processor Interface (CAPI) Storage, Networking and Analytics Programming (SNAP) framework, Alpha-Data and MLE show first collaboration results on FPGA acceleration utilizing technology from German Fraunhofer Heinrich-Hertz Institute.

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PCIe Range Extension via Robust, Long Reach Protocol Tunnels

Presentation at PCI-SIG Developers Conference 2018 in Santa Clara, CA

Protocol tunnels based on technology from German Fraunhofer Heinrich-Hertz Institute can extend the reach of PCIe connectivityto build systems-of-systems, for example in automotive ECU networking.

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Heterogeneous Multi-Processing for Software-Defined Multi-Tiered Storage Architectures

Presentation at the SNIA Storage Developers Conference 2017 in Santa Clara, CA.

A Xilinx Zynq Ultrascale+ based hybrid memory system mixing NVMe drives and DRAM to deliver multi-terabyte object store at 10 GigE line rate utilizing Key-Value-Store and TCP/IP Full Accelerators.

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PXI Express over IP

Published article in the current edition of

PXI Express over IP allows the connection of PXI-Modules with existing ethernet networks. It is based on the technology of Fraunhofer HHI for processing TCP/IP via FPGA-logic. With this technology it is possible to transmit PCIe-Transaction-Layer-Packages over TCP/IP. The following implementation shows the proof of concept. 

PXI Express over IP ermöglicht die Verbindung von PXI-Modulen über vorhandene Ethernet-Netze. Basierend auf der Technologie vom Fraunhofer HHI zur Verarbeitung von TCP/IP in FPGA-Logik werden PCIe-Transaction-Layer-Pakete über TCP/IP getunnelt. Eine beispielhafte Implementierung zeigt die Machbarkeit dieses Konzeptes.

Read the full article here.