10 GigE TCP/IP Stack for High-Speed Camera Transport
Presentation at FPGA Conference Europe in Munich, Germany, July 5-7, 2022
MLE presents NPAP, a TCP/IP full accelerator from Fraunhofer HHI, for use in Multi-Gigabit High-Speed Camera Image Transport. With increasing resolution and faster frame-rates in cameras and other image sensors, current standards such as GigEVision are running out of steam. Furthermore, modern "down-stream" image processing based on Artificial Intelligence relies on loss-less transport of pixels, lines and entire image frames. This presentation goes into the details of TCP/IP as a reliable, loss-less transport and closes with an implementation example using MicroChip PolarFire FPGA.
Zone-Based Automotive-Backbones
Presentation at Automotive Ethernet Congress in Munich, Germany, June 1-2, 2022
Fraunhofer IPMS and MLE present a joint work on how to combine TSN Ethernet and TCP/IP as an ultra-reliable deterministic low-latency transport for tunneling PCIe and other protocols for long-reach. Ethernet has emerged as the connectivity technology of choice. Since real-time networks are particularly necessary for security-critical applications such as ADAS, the emerging IEEE standard “Time Sensitive Networking” becomes an ideal network. Automotive Zone Gateways can be linked together via TSN implementing real-time automotive 10G/25G Ethernet. This creates a need for “tunneling” PCIe over TSN, supporting CPU-to-CPU communication (PCIe NTB) and NVMe storage. Through the use of TSN, data rates of 10 & 25 Gbit / s in the backbone and the high degree of integration of the solution, large amounts of data can be transported and, at the same time, time-critical data traffic with guaranteed latencies can be separated from less time-critical or background data traffic.
Platform Choices for FPGA-Based In-Network Compute Acceleration
Presentation at SmartNICsSummit 2022, April 26-28, 2022
FPGA-based SmartNICs can provide significant benefits by offloading network data processing off of CPU cores, data-in-motion processing, effectively enabling In-Network Compute. However, FPGA programming requires special skill sets to render predictable quality results. Open and open-source platforms such as NPAP or CORUNDUM or AMD OpenNIC or Intel IOFS can reduce the costs and risks when implementing FPGA-based SmartNICs. This is a joint presentation between MLE and UC San Diego, Dr. Alex Forencich.
CORUNDUM - From a NIC to a Platform for In-Network Compute
Presentation at FOSDEM'22, February 5-6, 2022
This joint presentation between Alex Forencich, UC San Diego, and Ulrich Langenbach, MLE, provides an introduction to the corundum project, implementing a 100 GbE NIC based on Commercial-off-the-shelf (COTS) FPGA cards, e.g. Xilinx Alveo. The project consists of all necessary RTL components, e.g. PCIe DMA engine, NIC datapath, MAC, PHY and integration of vendor specific IP cores, such as transceivers and PCIe hard-IP cores. In combination with the provided driver and debugging utility the ready-to-experiment state just requires a supported FPGA card + compiler to kick-off playing with the project.
Zone-Based Automotive Backbones Tunneling PCIe
Presentation at PCI-SIG Virtual Developers Conference 2021, May 25-26
The need for more safe and eco-friendly vehicles drives automotive connectivity towards so-called Zone-Based Architectures. Inside those so-called Zone Gateways PCIe technology provides the connectivity between multiple System-on-Chip (SoC), CPUs, GPUs, and FPGAs for scalable performance. Within the automotive network, multiple Zone Gateways connect with each other via the emerging IEEE standards “Time Sensitive Networking” (TSN).
Today, Fraunhofer and MLE can provide a working proof-of-concept in form of a digital circuit & system stack which encapsulates and decapsulates PCIe packets (and other protocols) over real-time automotive TSN Ethernet and which scales up to 100 Gbps.
PCIe-over-TCP-over-TSN-over-10/25GigE
Presentation at 4th Workshop "Programmable Processing for the Autonomous / Connected Vehicle", Sept. 24, 2020 at TH Ulm, Germany
ADAS and Autonomous Driving push the migration towards Zone-based architectures, which again push for more bandwidth and real-time capabilities in the Automotive Network. Based on open IEEE standards and a unique combination of technology from Fraunhofer Heinrich-Hertz-Institute, from Fraunhofer Institute for Photonic Microsystems and from Missing Link Electronics, PCI Express, and other protocols, can be transported in real-time at datarates of 10 Gbps, and more.
Security / Trusted Execution Environment and Functional Safety with Zync Ultrascale+ MPSoC / RFSoC
Presentation at the Workshop Programmable Processing for the Autonomous / Connected Vehicle 2019 in Neu-Ulm
The security of Embedded Systems has become a key concern, especially when hacked or tampered systems create safety issues and can harm people. In order to make an embedded system secure, CPU vendors like ARM offer the TrustZone technology. On top of this ARM TrustZone technology sits Open Portable (OP)-Trusted Execution Environment (TEE), an open source implementation of the TEE.
OP-TEE is a small secure operating system which, after authentication and description, gets loaded in an secured area in the memory. A Rich OS (e.g. Xilinx PetaLinux) driver can request, via a Secure Monitor Call, the execution of a trusted application. MLE took the effort to port OP-TEE to Xilinx Zync UltraScale+ MPSoC Platform, including device specific optimizations.
Sensor Fusion and Data-in-Motion Processing for Autonomous Vehicles
Presentation at PCI-SIG Developers Conference 2019 in Santa Clara, CA
Using PCIe Non-Transparent Bridging to connect multiple CPUs/GPUs/SoCs/FPGAs within an automotive ECU. This heterogeneous architecture meets tight Size-Weight-and-Power requirements and combines processing flexibility with sufficient bandwidth at deterministic low latency to run algorithms from classical image processing over Deep-Learning to real-time control algorithms.
Network Protocol Acceleration with CAPI SNAP
Presentation at IBM OpenPOWER Summit Europe 2018 in Amsterdam, NL.
Addressing Network Protocol Acceleration for IBM OpenPOWER Power8 and Power9 with the Coherent Accelerator Processor Interface (CAPI) Storage, Networking and Analytics Programming (SNAP) framework, Alpha-Data and MLE show first collaboration results on FPGA acceleration utilizing technology from German Fraunhofer Heinrich-Hertz Institute.
PCIe Range Extension via Robust, Long Reach Protocol Tunnels
Presentation at PCI-SIG Developers Conference 2018 in Santa Clara, CA
Protocol tunnels based on technology from German Fraunhofer Heinrich-Hertz Institute can extend the reach of PCIe connectivityto build systems-of-systems, for example in automotive ECU networking.