Missing Link Electronics

MLE Releases NVMe Streamer

MLE releases NVMe Streamer which is a so-called Full Accelerator NVMe host subsystem integrated into FPGAs. NVMe Streamer offloads the NVMe protocol into programmable logic and enables to stream data from FPGA blocks in and out of directly-attached NVMe SSDs.

US Patent 10,509,880 for Design Automation for Configurable Mixed-Signal Systems

Missing Link Electronics has been awarded another patent in the field of mixed-signal: US Patent 10,509,880 B2 was issued DEC 17 2019 and claims novel Electronic Design Automation (EDA) methods for Sigma-Delta Modulation in FPGA-based Mixed-Signal Systems enabling Analog FPGA I/O.

MLE Open-Sources Build System for Xilinx Vivado

To facilitate an FPGA Build Environment which can be automated, for example for Continuous Integration (CI), and which ensures fully reproducible results later in the development and product lifecycle, the Team at Missing Link Electronics has put together a collection of scripts. Currently focused on the Xilinx Vivado toolchain (Version 2016.4 or newer) and tested under Ubuntu Linux 16.04 LTS and 18.04 LTS, this scripted FPGA Build Environment has recently been made available at GitHub (https://github.com/missinglinkelectronics/vivado-build-system ) under open source Apache 2.0 license. 

Team MLE welcomes any feedback and contribution from the FPGA ecosystem!

MLE Presents Xilinx Alveo-based Acceleration for Automotive Test Equipment

November 12-13, 2019, Missing Link Electronics, a Xilinx Alveo Independent Software Vendor (ISV), exhibits at the Xilinx Developers Forum Europe (XDF). Alveo Accelerators for Key-Value-Store (KVS), Data-in-Motion labelling, compression and encryption facilitate ADAS / Autonomous Vehicle AI-in-the-Loop testing at speeds of 100 Gbps. Please stop by and visit us.

MLE Silver Sponsor of Xilinx Developers Forum 2019 in San Jose, CA

October 1-2, 2019, Missing Link Electronics is a Silver Sponsor of the Xilinx Developers Forum (XDF) in San Jose, CA, where we will be presenting solutions for FPGA Acceleration and for Security / ARM Trusted Execution Environment (OP-TEE). Please stop by and visit us at Booth 35. 

3rd Workshop "Programmable Processing for the Autonomous / Connected Vehicle"

On July 17th 2019 the 3rd workshop on using FPGAs and ACAP for automotive ADAS and autonomous vehicles took place. Once more it was an excellent event with high-quality presentations and participants who showed great interest.

Click here to get an impression of our third workshop and please follow this link for the proceedings.

Lunch & Learn at EDA Direct Tuesday June 25th, 2019

MLE will participate in "Designing High-Performance ECU and Signal Integrity Analysis in Autonomous Vehicles" at a Lunch & Learn organized by EDA Direct.

Read the MLE Technical Brief Tool Options When Debugging an FPGA-Based ECU for Autonomous Driving.

Presentation at PCI-SIG Developers Conference 2019

MLE presents "Sensor Fusion and Data-in-Motion Processing for Autonomous Vehicles" at the PCI-SIG Developers Conference 2019.

 (download slides) or visit our technical publications.

MLE Featured Premier Xilinx Alliance Partner

Xilinx features Missing Link Electronics as a Premier Partner offering IP, Design Services and Software for key markets Aerospace & Defense, Automotive, Data Center, Industrial, Wired Communications, Wireless Communication.

Solutions and services from Missing Link Electronics include Security (OP-TEE), crypto subsystems, connectivity (PCIe, Ethernet, USB, SATA, NVMe) IP integration, camera/lidar/radar data acquisition and aggregation processing, Functional Safety, TCP/UDP/IP Full Accelerators, Key-Value-Store Accelerators, Digital Signal Processing IP (PAM/QAM Multi-format mapper, OFDM transmitter, WOLA channelizer, Adaptive time-domain equalizer, FFT), PetaLinux Design Service.

Embedded World Exhibition 2019 - Xilinx Booth

TUE FEB 26 - THU FEB 28 - Exhibition Nuremberg - live demo at the Xilinx Booth

Booth 3A-235: Zync UltraScale+ RFPSoC – Software Defined Radio

This Software Defined Radio demonstration showcases the Zynq® UltraScale+™ RDSoC multi-giga-sample RF data converters, and soft-decision forward error correction (SD-FEC), integrated into a SoC architecture. Complete with an ARM® Cortex™-A53 processing subsystem, UltraScale+ programmable logic, and the highest signal processing bandwith in a Zynq UltraScale+ device, this family provides a comprehensive FR signal chain for wireless, cable access, test & measurement, early warning / radar, and other high performance FR applications.