Network Element Virtualization Whitepaper

SmartNICs Make Better Networks! At SmartNICsSummit 2022, held April 26-28 in the Doubletree Hotel in San Jose, CA, Algoblu and MLE will present solutions for NEV and the use case of low-latency application. For more details, please read the joint whitepaper "Network Element Virtualization". With a foreword by Awanish Verma, Principal Architect and Director in the newly formed Data Center and Communications Group (DCCG) at AMD, Algoblu, a NaaS provider, and Missing Link Electronics, a premier partner in Xilinx Alliance ecosystem, will show how they use FPGA technology to implement Network Element Virtualization (NEV) to accelerate SD-WAN adoption.


MLE Presents at FPGA Conference Europe 2022

At FPGA Conference Europe 2022, MLE will present "A 10 Gigabit Ethernet TCP/IP Stack Implementation on Microsemi PolarFire for High-Speed Camera Image Transport" and will give details on FPGA-based TCP/UDP/IP Full Acceleration for camera based system. FPGA Conference Europe 2022 is organized by fellow Xilinx Alliance member PLC2 and will take place July 5-7, 2022 at the NH München Ost Conference Center.


MLE NPAC-40G Now Runs CORUNDUM System Stack

MLE has ported and tested a full system stack based on CORUNDUM for NPAC-KETCH, CORUNDUM is a vendor-neutral open source high-performance FPGA-based SmartNIC development platform. NPAC-KETCH is a FHHL PCIe card featuring 4 SFP+ ports for 10 Gigabit Ethernet, PCIe 3.1 8 GT/sec x8 lanes, and In-Network Processing using Intel's Stratix 10 GX 400 FPGA.


MLE NPAC-40G - A Cost-Efficient PCIe SmartNIC Solution

MLE has partnered with Fraunhofer HHI and Elemaster Germany to provide the industry-proven TCP/UDP/IP Network Protocol Accelerator Platform (NPAP) in form of NPAC-40G, a PCIe Network Protocol Accelerator Card. NPAC-40G implements reliable high-bandwidth low-latency TCP/UDP/IP transport plus Linux PCIe stream drivers and, optionally, can run customizable In-Network Processing using the Intel's Stratix 10 GX 400 FPGA.


MLE Releases NPAP TCP/UDP/IP Stack Version 1.8.0

MLE has released Version 1.8.0 of NPAP, the TCP/UDP/IP Full Accelerator from Fraunhofer HHI. Changes include fixes for UDP, padding for Ethernet frames smaller than 60 Bytes and an increase of the maximum number of TCP Session instances. Please refer to the updated datasheet MLE TB20220408 for more information.


CORUNDUM Project Releases AMD/Xilinx Zynq MPSoC Support

CORUNDUM, the open source In-Network Compute Platform hosted on Github now supports the integrated ARM A53 Processing System of AMD/Xilinx Zynq UltraScale+ MPSoC FPGA. Based on key contributions from MLE this work allows implementing complete Linux subsystems running within the SmartNIC, separate and independent from the underlying host operating system. Work was tested using the Sidewinder-100 card from Fidus Systems, a fellow AMD/Xilinx Alliance member.


MLE Integrates CORUNDUM MQNIC Support into DPDK

MLE has integrated support for the CORUNDUM project's MQNIC into the open source Data Plane Development Kit. MQNIC is the open source network interface card within CORUNDUM, the open source FPGA-based In-Network Compute Platform. DPDK now has support for a single interface and a single port per interface of MQNIC. MLE work was tested with a 10G version of MQNIC build for the Fidus Sidewinder-100 board which features an AMD/Xilinx Zynq UltraScale+ MPSoC ZU19EG.


MLE Presents at SmartNICsSummit 2022

At SmartNICsSummit 2022, MLE will present "Platform Choices for FPGA-Based In-Network Compute Acceleration" which is joint work with the Corundum project and Fraunhofer HHI. SmartNICs and Function Accelerator Cards address performance issues in Software-Defined Networking (SDN) as network port speeds increasingly outstrip CPU performance. SmartNICsSummit will be held April 26-28, 2022, in San Jose, CA.


MLE NVMe Streamer Passes PCIe 4.0 Testing

MLE has successfully tested NVMe Streamer a so-called Full Accelerator NVMe host subsystem for PCIe 4.0. Test setup was the Xilinx ZCU216 Development Kit featuring Zynq UltraScale+ RFSoC Gen3, and the new FPGA Drive FMC Gen4 from partner Opsero. The combined solution doubles bandwidth for modern PCIe Gen4 x4 M.2 NVMe SSD.


Fraunhofer IPMS and MLE Present at Automotive Ethernet Congress, June 1-2, 2022

At the Automotive Ethernet Congress 2022, on June 2nd we present "Zone-Based Automotive Backbone" a.k.a. Auto/TSN which is joint work between MLE and Fraunhofer IPMS on how to combine TSN Ethernet, TCP/IP as an ultra-reliable deterministic low-latency transport for tunneling PCIe and other protocols for long-reach. The joint presentation also features a lab car demo in which tunneling effects on bandwidth and latency within the network will be explained.