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MLE NVMe Streamer Passes PCIe 4.0 Testing

MLE has successfully tested NVMe Streamer a so-called Full Accelerator NVMe host subsystem for PCIe 4.0. Test setup was the Xilinx ZCU216 Development Kit featuring Zynq UltraScale+ RFSoC Gen3, and the new FPGA Drive FMC Gen4 from partner Opsero. The combined solution doubles bandwidth for modern PCIe Gen4 x4 M.2 NVMe SSD.


 

Fraunhofer IPMS and MLE Present at Automotive Ethernet Congress, June 1-2, 2022

At the Automotive Ethernet Congress 2022, on June 2nd we present "Zone-Based Automotive Backbone" a.k.a. Auto/TSN which is joint work between MLE and Fraunhofer IPMS on how to combine TSN Ethernet, TCP/IP as an ultra-reliable deterministic low-latency transport for tunneling PCIe and other protocols for long-reach. The joint presentation also features a lab car demo in which tunneling effects on bandwidth and latency within the network will be explained.


 

NPAP RTL Simulation Demonstrates Low-Latency TCP/IP

MLE has complemented NPAP, the TCP/UDP/IP Full Accelerator from Fraunhofer HHI, with an RTL Simulation environment for Xilinx Vivado ISim and for the Questa Advanced Simulator from Siemens EDA. This simulation environment is available free-of-charge to all licensees of NPAP with an active maintenance subscription. For more information please read the MLE Technical Brief TB20220305 titled "Latency Measurement of 10G/25G/50G/100G TCP-Cores Using RTL Simulation".


 

MLE & Intel PSG Optimize NPAP for Intel HyperFlex Architecture

As the outcome of joint engineering collaboration between Intel PSG and MLE Germany, an new version of NPAP, the TCP/UDP/IP Full Accelerator from Fraunhofer HHI was released by MLE. This release incorporates many code optimizations for utilizing the Intel HyperFlex technology. Intel HyperFlex FPGA Architecture addresses increased bandwidth demands via improved FPGA logic clocking. For a typical NPAP setup clock speed was improved by more than 1.5x to currently over 500 MHz. Because of NPAP's unique 128-bit wide datapath architecture, this enables more than 60 Gbps line rates. NPAP-100G for Intel Hyperflex is made available by MLE as a licensable subsystem stack or as a Function Accelerator Card based on Stratix 10GX devices.


 

MLE Presents CORUNDUM In-Network Compute at FOSDEM'22

At FOSDEM'22, an annual event to promote the widespread use of free and open source software, MLE co-presents an update of the CORUNDUM.io project. CORUNDUM is an open-source project hosted at Github for building high-performance FPGA-based Network-Interface Cards (NIC) or in-network compute platforms / SmartNICs. MLE's work includes enhanced support for Xilinx Zynq UltraScale+ MPSoC, for example interfacing with Linux running on the ARM-based Processing System (PS). Read more on the work presented...


 

DEC and MLE Collaborate on Multi-RAID SSD NVMe Streamer System

Today DEC (Defense Engineering Corporation, Beavercreek, OH USA) and MLE (Missing Link Electronics, Inc., San Jose, CA USA) announced they have collaborated to develop a high performance, Multi-RAID SSD Streaming System to incorporate into high performance data recording systems for the US Defense Dept. The system will be provided by DEC.

Dan Whitehead adds: “DEC is a Government Contractor working with the US Defense Dept. When we needed to develop a fast, SSD multi-RAID NVMe streamer for one of our projects, we became aware of Missing Link Electronics by way of Xilinx’s Premier Partners Program. This project required advanced knowledge of both specialized hardware and communication protocols to meet our customers exacting requirements. MLE came in, evaluated our needs, and developed the technical design using their own NVMe IP and in-depth hardware and software expertise to provide, on time and on budget, a board level solution to integrate into our system design. MLE provided unique benefit by having great access to our supplier’s technology, advanced IP, and specialized, hands-on expertise. I recommend MLE to others needing advanced expertise in programmable hardware and software design. Working with them is a pleasure and produces excellent results.”

Andreas Schuler, MLE Product Engineering, commented: “When we were approached by DEC we were happy to see that our long-time affiliation with the Xilinx Premier Partners Program provided a challenging opportunity to work with a top-notch engineering team at DEC. We were successfully able to combine our NVMe Streamer technology with DEC’s expertise in providing system-level technology to the US Defense Department. This produced an excellent result in which both companies take pride.”

DEC specializes in advanced sensor and processing technologies for Intelligence, Surveillance, and Reconnaissance (ISR), Unmanned Systems, and Self-Protection applications for the defense industry.

MLE is an intellectual property (IP) and software and hardware design services company based in San Jose, CA. It is a proud member of the Xilinx Premier Partners Program. MLE utilizes an extensive catalog of in-house developed IP for network connectivity, storage protocols and I/O interfaces for programmable platforms in its work. It develops solutions for international commercial, automotive, and Defense and Aerospace customers.


 

MLE Releases NPAP for MicroSemi PolarFire

In response to customer requests, MLE has ported NPAP-10G, the low-latency TCP/UDP/IP Full Accelerator for 10 Gigabit Ethernet to MicroSemi PolarFire FPGAs. MLE is now working with partner MicroSemi and a first customer to optimize NPAP-10G for sensor Edge Applications.


 

MLE Becomes Premier MicroSemi Design Partner

MLE has joined the Microchip Ecosystem as a Premier Design Partner. "Our customers have asked us to extend MLE's design services to include MicroSemi's FPGA families. In particular for industrial applications MicroSemi's PolarFire seems to provide a great combination of longterm availability, cost-efficiency and high-speed I/Os needed for PCIe and/or 10 Gigabit Ethernet.", says Endric Schubert, CTO and Co-Founder.


 

MLE Supports PCO with NPAP for Camera Systems

MLE has been providing to PCO a connectivity solution based on the Network Protocol Acceleration Platform from Fraunhofer HHI. The key objective is to scale along with increasing image sensor resolutions and frame rates and to provide reliable image transfers - using the well-known TCP/IP protocol - from FPGAs to standard server equipment with data rates up to 100 Gbps. Read more in this joint publication (German).


 

MLE Joins Github Project CORUNDUM for In-Network Compute

CORUNDUM.io is an open-source project hosted at Github for building high-performance FPGA-based Network-Interface Cards (NIC) or in-network compute platforms / SmartNICs. "Our motivation for joining is to build better and more cost-effective SmartNIC solutions by complementing FPGA Full Acceleration using NPAP, the TCP/IP Stack that I started at Fraunhofer HHI, with a performance oriented hardware/software infrastructure", says Ulrich Langenbach, Director Engineering at Missing Link Electronics. Engineering work plans include enhancing support for Xilinx Zynq UltraScale+ MPSoC and for porting CORUNDUM to some of MLE's partners' FPGA boards.