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MLE exhibits at SC22

Partner ProDesign and MLE will showcase High-Performance Compute solutions at Super Computing Conference SC22. To address the acceleration needs of Disaggregated Computational Storage, ElasticSearch, or At-Speed In-Network Processing the featured solutions integrate MLE's FPGA-based networking and storage accelerators with ProDesign's FALCON 1SM21 HPC Card (based on Intel Stratix 10 MX/NX FPGA) and ProDesign's HAWK VC1902 HPC Card (based on AMD/Xilinx Versal FPGA). Also featured will be Homa, a reliable, rapid request-response protocol (RRRRP) from Stanford University professor John Ousterhout. SC22 is held November 13-18 in the Kay Bailey Hutchinson Convention Center Dallas, TX.


MLE Presents at SNIA SDC 2022

At SNIA Storage Developers Conference (SDC) 2022, on Sept. 14, MLE and partner Fraunhofer IPMS will present "Converging PCIe and TSN Ethernet for Composable Infrastructure in High-Performance In-Vehicle Embedded Systems": While the needs for storage in automotive are somewhat relaxed, compared to datacenters, automotive has a need for “unconventional” storage connectivity like many sensors to few CPUs to single SSD. And, unlike datacenters, automotive comes with strong constraints for size, weight and power, and real-time guaranties. Time-Sensitive Networking (TSN) is one of the best positioned options for in-vehicle networking. In combination with reliable transports such as TCP/IP this enables deterministic networking for distributed systems. MLE presents the needs of modern automotive networking and storage architectures, and approaches for converging (real-time) Ethernet and PCIe as a common fabric for reliable and cost-efficient implementations.


US Patent 11,356,388 for Real-Time Multi-Protocol Heterogeneous Packet-Based Transport

Missing Link Electronics has been awarded US Patent 11,356,388 on Real-Time Multi-Protocol Heterogeneous Packet-Based Transport which covers real-time and time-synchronization aspects when tunneling packets such as PCI Express (PCIe) Transaction-Layer Packets (TLP) over reliable TCP/IP over 1/10/25/50/100G Ethernet. This extends the range of PCIe and enables building distributed systems based on PCIe, or other packed-based protocols.


Network Element Virtualization Whitepaper

SmartNICs Make Better Networks! At SmartNICsSummit 2022, held April 26-28 in the Doubletree Hotel in San Jose, CA, Algoblu and MLE will present solutions for NEV and the use case of low-latency application. For more details, please read the joint whitepaper "Network Element Virtualization". With a foreword by Awanish Verma, Principal Architect and Director in the newly formed Data Center and Communications Group (DCCG) at AMD, Algoblu, a NaaS provider, and Missing Link Electronics, a premier partner in Xilinx Alliance ecosystem, will show how they use FPGA technology to implement Network Element Virtualization (NEV) to accelerate SD-WAN adoption.


MLE Presents at FPGA Conference Europe 2022

At FPGA Conference Europe 2022, MLE will present "A 10 Gigabit Ethernet TCP/IP Stack Implementation on Microsemi PolarFire for High-Speed Camera Image Transport" and will give details on FPGA-based TCP/UDP/IP Full Acceleration for camera based system. FPGA Conference Europe 2022 is organized by fellow Xilinx Alliance member PLC2 and will take place July 5-7, 2022 at the NH München Ost Conference Center.


MLE NPAC-40G Now Runs CORUNDUM System Stack

MLE has ported and tested a full system stack based on CORUNDUM for NPAC-KETCH, CORUNDUM is a vendor-neutral open source high-performance FPGA-based SmartNIC development platform. NPAC-KETCH is a FHHL PCIe card featuring 4 SFP+ ports for 10 Gigabit Ethernet, PCIe 3.1 8 GT/sec x8 lanes, and In-Network Processing using Intel's Stratix 10 GX 400 FPGA.


MLE NPAC-40G - A Cost-Efficient PCIe SmartNIC Solution

MLE has partnered with Fraunhofer HHI and Elemaster Germany to provide the industry-proven TCP/UDP/IP Network Protocol Accelerator Platform (NPAP) in form of NPAC-40G, a PCIe Network Protocol Accelerator Card. NPAC-40G implements reliable high-bandwidth low-latency TCP/UDP/IP transport plus Linux PCIe stream drivers and, optionally, can run customizable In-Network Processing using the Intel's Stratix 10 GX 400 FPGA.


MLE Releases NPAP TCP/UDP/IP Stack Version 1.8.0

MLE has released Version 1.8.0 of NPAP, the TCP/UDP/IP Full Accelerator from Fraunhofer HHI. Changes include fixes for UDP, padding for Ethernet frames smaller than 60 Bytes and an increase of the maximum number of TCP Session instances. Please refer to the updated datasheet MLE TB20220408 for more information.


CORUNDUM Project Releases AMD/Xilinx Zynq MPSoC Support

CORUNDUM, the open source In-Network Compute Platform hosted on Github now supports the integrated ARM A53 Processing System of AMD/Xilinx Zynq UltraScale+ MPSoC FPGA. Based on key contributions from MLE this work allows implementing complete Linux subsystems running within the SmartNIC, separate and independent from the underlying host operating system. Work was tested using the Sidewinder-100 card from Fidus Systems, a fellow AMD/Xilinx Alliance member.


MLE Integrates CORUNDUM MQNIC Support into DPDK

MLE has integrated support for the CORUNDUM project's MQNIC into the open source Data Plane Development Kit. MQNIC is the open source network interface card within CORUNDUM, the open source FPGA-based In-Network Compute Platform. DPDK now has support for a single interface and a single port per interface of MQNIC. MLE work was tested with a 10G version of MQNIC build for the Fidus Sidewinder-100 board which features an AMD/Xilinx Zynq UltraScale+ MPSoC ZU19EG.