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      MLE & Intel PSG Optimize NPAP for Intel HyperFlex Architecture

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      As the outcome of joint engineering collaboration between Intel PSG and MLE Germany, an new version of NPAP, the TCP/UDP/IP Full Accelerator from Fraunhofer HHI was released by MLE. This release incorporates many code optimizations for utilizing the Intel HyperFlex technology. Intel HyperFlex FPGA Architecture addresses increased bandwidth demands via improved FPGA logic clocking. For a typical NPAP setup clock speed was improved by more than 1.5x to currently over 500 MHz. Because of NPAP's unique 128-bit wide datapath architecture, this enables more than 60 Gbps line rates. NPAP-100G for Intel Hyperflex is made available by MLE as a licensable subsystem stack or as a Function Accelerator Card based on Stratix 10GX devices.