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      Auto/RPS DevKit

      , , ,

      Automotive Rapid Prototyping System (Auto/RPS)

      MLE provides an FPGA-based Rapid Prototyping System (RPS) catering to the specific needs of automotive engineers designing next-generation Zone Based Architectures.

      MLE Auto/RPS enables automotive system engineers to design and to validate software-defined vehicle (SDV) functions along with MLE Auto/TSN in-vehicle networking. 

      MLE Auto/RPS was designed as a shortcut into A-sample hardware development of Zonal Gateways / ECUs and implements an FPGA Full System Stack based on the Trenz Electronic TE0950-02 SoC-FPGA Development Kit featuring the AMD Versal AI Edge FPGA, and an automotive FPGA subsystem from MLE.

      Inquire Now
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      Features and Benefits

      • Based on open standards and open-source software
      • Support for multiple, different sensor inputs
      • Backbone connectivity up to 100 Gbps
      • Open-source real-time operating systems 
      • Multi-core ARM processing system
      • Flexible, adaptable FPGA design for implementing data acquisition and data preprocessing (DADP)
      • Supports Secure OTA via ARM OP-TEE Trusted Execution Environment (optional)

      IO Interfaces

      • 12 V DC power supply
      • 1 Gig Ethernet
      • USB 2.0 for JTAG and console
      • 2x ports for 25G Ethernet (up to 4 ports optional)
      • MIPI CSI-2 x2 Camera Input (optional)
      • GMSL (via optional adapter AD-GMSL2ETH-SL)
      • Up to 2x CAN-FD (via CRUVI HS) (optional)
      • Up to 2x CAN 2.0B (via CRUVI HS) (optional)
      • PCIe 4.0 x4 NVMe M.2 SSD via Opsero FMC with 4x GTYP for (optional)

      Processing Functionality

      • Dual-core ARM Cortex A72
      • Dual-core ARM Cortex R5F
      • 8 GB DDR4 DRAM
      • 128 MByte SPI Flash (primary boot option)
      • 32 GB eMMC (secondary boot option)
      • MicroSD Card (for Linux root file system, for example)
      • 150k LUTs
      • 464 DSP Engines 
      • 34 AI Engines-ML with up to 45 TOPS INT8
      Industrial Networking Acceleration FPGA Subsystem - Processing Functionality

      Dual-Core ARM Cortex-A72 Software Environment

      • Ubuntu 2024.04 LTS (pre-installed)
      • Linux OS Debian 12 PREEMPT_RT (optional)
      • Yocto project design flow (optional)
      • AMD/Xilinx Petalinux (optional)
      AMD Versal Portfolio
      https://www.xilinx.com/products/design-tools/embedded-software.html

      Dual-Core ARM Cortex-R5F Software Environment (optional)

      • FreeRTOS (optional)
      Dual-Core ARM Cortex-R5F Software Architecture

      FPGA System Block Diagram

      Industrial Networking Acceleration FPGA Subsystem - Block Diagram

      FPGA Development Kit

      Auto/RPS-TE-0950-25G

      • Hardware based on  TE0950 AMD Versal™ AI Edge Evalboard from Trenz Electronic
      • Features the AMD Versal™ AI Edge VE2302-1LSE
      • FPGA Full System Stack for MLE Auto/TSN 2x25G
      • Ubuntu 24.04 LTS for ARM
      • Customized MLE Auto/TSN Linux kernel 6.6.10
      • 12 VDC for lab and table top operation

      Pricing and Availability

      Product NameDeliverablesExample Pricing
      Rapid Prototyping System (Base) AUTORPS-TE-0950-25GFPGA Full System Stack for MLE Auto/TSN stack for 2x 25 GigE comprising hardware (FPGA board, power supply, active cooling, enclosure), system FPGA config (bitfile and rootfs).

      $3,880,- per unit ( MOQ 2 units)
      Purchase at Trenz Electronics Shop

      System FPGA Development KitAMD/Xilinx Vivado Design Project plus Commercial Single-Project-Use License delivered as encrypted netlists or RTL.Please Inquire
      Application-specific R&D ServicesAdvanced FPGA design services with access to acceleration experts from MLE.$1,880.- per engineering day (or fixed price project fee)
      Inquire Now
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      Documentation

      100/200/400G Fast FPGA RAID (FFRAID)

      , , , ,

      FFRAID
      100/200/400G Fast FPGA RAID

      MLE Fast FPGA RAID - FFRAID_600x200

      FFRAID: Accelerate NVMe FPGA RAID Data Recording and Replay

      Some High-Speed Data Acquisition Systems do require storing the data in non-volatile memory. For those cases where the read/write data rate exceeds the capabilities of even the highest performance NVMe SSDs, MLE has developed an NVMe Fast FPGA RAID (FFRAID) solution:

      100_200_400G Fast FPGA RAID (FFRAID) Data Recorder Application Scenario
      MLE’s 400G Fast FPGA RAID (FFRAID) can transfer bulky data from multiple sensors to the NVMe RAID SSD at the speed up to 400Gbps. It supports channel aggregation of multiple protocols from different input sources, and each channel has its dedicated engine and storage space.

      Now, you can transfer bulky data from multiple sensors to a RAID of NVMe SSDs at speeds up to 400 Gbps. MLE’s Fast FPGA RAID implements a channel-based architecture, supports data-in-motion pre- and post-processing and is highly scalable with regards to bandwidth and recording capacity. Multiple systems can further be cascaded via high-accuracy IEEE time-synchronization for faster or deeper recording.

      Adaptable signal front-ends support many different I/O standards in a “mix & match” fashion. 

      MLE’s Fast FPGA RAID is compatible with Linux Software-RAID (via the Linux MD driver). This allows recording at high data rates and replaying at slower speeds, or vice versa.

      Channel-based Architecture of Fast FPGA RAID (FFRAID)

      MLE’s Fast FPGA RAID (FFRAID) implements a channel-based architecture where each data source/sink can be associated with a dedicated RAID engine and a dedicated storage space. Each channel can have 10/25/50/75/100 Gbps, or combinations thereof.

      This channel-based architecture along with the combination of FPGA NVMe Recording Stack plus a well-tuned PCIe setup, delivers a best-in-class price/performance ratio for high-speed data acquisition, recording and replay. MLE’s multi-core NVMe Host Controller Subsystem supports dedicated NVMe queues per SSD in a PCIe Peer-to-Peer communication.

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      Applications

        • Autonomous Vehicle Path Record & Replay
        • Automotive / Medical / Industrial Test Equipment
        • High-speed Radar / Lidar / Camera Data Acquisition & Storage
        • Very Deep Network Packet Capture of Ethernet or IPv4 or TCP/UDP Data

      Key Features

        • Scalable from 100Gbps to 400Gbps
        • Cascading of multiple systems with time-sync
        • Start-Pause-Stop Data Recording
        • Pre-trigger Data Recording in circular buffers
        • Adaptable signal front-ends
        • Read/write compatible with Linux Software-RAID

      Scalability

      MLE’s Fast FPGA RAID supports a wide range of NVMe SSDs and can be scaled from M.2 SSDs for small and light-weight embedded systems up to large 19” racks using high-performance U.2 or U.3 SSDs. Scalability also includes selecting from different SSD capacities and Drive-Writes-per-Day (DWPD) models. Here a table of possible recording times in minutes:

       Recording Speed (Gbps)
      Storage (TiB) 100150200250300350400
      57.24.83.62.92.421.8
      1014.39.57.25.74.84.13.6
      1521.514.310.78.67.26.15.4
      2028.619.114.311.59.58.27.2
      2535.823.917.914.311.910.28.9
      3042.928.621.517.214.312.310.7
      3550.133.425.120.016.714.312.5
      4057.338.228.622.919.116.414.3
      4564.442.932.225.821.518.416.1
      5071.647.735.828.623.920.517.9
      Recording Time in Minute(s)

      FFRAID High Speed Data Recording Use Cases

      Besides record/replay of raw data we support data-in-motion pre- and post-processing that enables you to add your custom algorithms for indexing and metadata generation, on-the-fly data decimation, or running in “spy-mode” as a transparent data proxy.

      • Ingress data from the high-speed sensors are transferred and recorded at-speed and as-is onto the Fast FPGA RAID.
      MLE400G NVMe RAID FPGA-based data recorder - Raw Data Recording
      • Communication from a high-speed data source can be transported to a data sink while this data is also recorded at-speed.
      MLE400G NVMe RAID FPGA-based data recorder - Raw Data Recording
      • Unwanted pieces of the ingress data is removed on-the-fly prior to storage. This can, for example, be a selection of certain regions-of-interest (ROI).
      • Ingress data can be analyzed on-the-fly to generate indexing information for later search, for example. This metadata is then recorded along with the ingress data. Metadata can, for example, be: Hardware timestamps, regions-of-interest, search indexes.
      MLE 400G NVMe RAID FPGA-based data recorder - Indexing and Metadata

      Exemplary Evaluation Reference Design of Fast FPGA RAID (FFRAID)

      The implementation example of MLE 100/200/400G Fast FPGA RAID is built with AMD EPYC server-grade motherboard, NVMe FPGA RAID cards, and U.3 SSDs. This evaluation reference design is available now for testing with your front-end devices or SSDs.

      Test with Your Front-End Device Now!

      Request Testing
      MLE 400G Fast FPGA RAID (FFRAID) - Evaluation Reference Design for Testing Front-End Device
      MLE 400G Fast FPGA RAID (FFRAID) - Evaluation Reference Design for Testing SSDs

      Test with Your SSDs Now!

      Request Testing

      Pricing

      MLE’s license fee structure reflects the needs for best-in-class price/performance ratio for 100/200/400G Fast FPGA RAID:

      Product Name DeliverablesExample Pricing

      Evaluation Reference Design (ERD)

      Available upon request as FPGA design project, with optional customizations (different target device, different transceivers, etc)

      Upon Request

      Inquire

      Turnkey System

      Completely hardware-software integrated ready-to-use system, available sizes from medium-sized embedded PC to 19″ rack mount, lab-use or ruggedized. You can bring your own SSDs, or choose SSDs from our many options depending on the storage capacity required.

      Starting at $14,800.- (depends on FPGA device, line rate, and SSDs)

      Inquire

      Fast FPGA RAID Card

      Fast FPGA RAID Card based on off-the-shelf 3rd party FPGA cards, including AMD Alveo U50 / U55C with Ultrascale+ and HBM, AMD Alveo V80 with Versal and HBM, and Intel/Altera Agilex 7 AGF014 with DDR4.

      Starting at $8,000.-

      Inquire 

      Inquire Now
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      Documentation

      Frequently Asked Questions​

      No, the MLE 100/200/400G Fast FPGA RAID data recorder is so-called Block Storage. So, no file systems are not supported. For each data transfer the user application logic selects a start and maximum end address, and then data is written to flash in a linear fashion. This achieves best performance and avoids write amplifications.

      Partitions are not explicitly supported. However, the user application logic can use the 100/200/400G Fast FPGA RAID data recorder to read the SSD’s partition table and then set up transfers with start and maximum end address to be aligned to partitions.

      Only one single namespace is supported per SSD.

      The standards for the 100/200/400G Fast FPGA RAID data recorder is 4/8/16 SSDs. The number of SSDs can be adjusted to your application within certain limits, for example: the accumulated sustained write speed should be faster then the incoming data stream, or to many SSDs can cause latency issues.  However, we can customize the 100/200/400G Fast FPGA RAID data recorder for your application to support more complex PCIe topologies. Please ask us for more details.

      The 100/200/400G Fast FPGA RAID data recorder currently supports one single IO Queue per SSD. This IO Queue can have up to 128 entries, each with up to 128 KiB data. I.e. you can have up to 16 MiB of “data in flight” per SSD. If needed, we can change the depth and size of this IO Queue. However, given the needs of streaming applications increasing the number of IO Queues may not be advantageous.

      Yes, this is supported. Peer-to-Peer transfers can be very attractive as it frees up the host CPU. Team MLE can customize the 100/200/400G Fast FPGA RAID data recorder for your application to support many more complex PCIe topologies, including multiple direct-attached SSDs, multiple SSDs connected via a 3rd party PCIe switch chip, including PCIe Peer-to-Peer. Please ask us for more details.

      The 100/200/400G Fast FPGA RAID data recorder can be configured via an AXI4-Lite register space which can also be handled by a provided Linux handler. This register space is also used to set up and control streaming transfers. The actual data exchange then is handled via an AXI4-Stream master and slave. Some GPIO style status signals for informational purposes, like LEDs, are provided as well. This is documented in our developers guide.

      Currently, the 100/200/400G Fast FPGA RAID (FFRAID) data recorder handles 16 independent data streams. To save resources, the number of streams can be reduced without loosing the overall performance by widening the data paths. 

      Yes. Because the 100/200/400G Fast FPGA RAID data recorder is agnostic to the formfactor of your SSD m.2, u.3/u.3, EDSFF and so on are supported, as long as your SSD “speaks the NVMe protocol” and not SATA nor SAS.

      While, again, the 100/200/400G Fast FPGA RAID (FFRAID) data recorder is compatible to work with any NVMe SSD, there are a couple of other aspects to keep in mind when selecting an NVMe SSD: Noise, vibration, harshness, temperature throttling, local RAM buffers, SLC, MLC, TLC, QLC, 3D-XPoint, etc. To enable our customers to deliver dependable performance solutions, we have worked with a set of 3rd party SSD vendors and would be happy to give you technical guidance in your project. Please inquire.

      Robo/TSN

      ,

      Robo/TSN
      Virtualized Industrial Networks

      Robo/TSN Virtualizing Industrial Networks

      Artificial Intelligence algorithms and machine vision with high-resolutions and fast frame-rates continue to drive towards higher bandwidth demands in real-time industrial network. At the same time lines between IT and OT start to blur as modern datacenter hardware can reduce TCO for OT equipment, significantly.

      Under the working title “Robo/TSN”, MLE and partners have developed network virtualization technology for multi-Gigabit TSN (Time Sensitive Networking). Solutions are based on open standards and include access points and SmartNICs which scales to 100 Gbps, and more. Use cases are:

        • Connect high speed sensors in the field with AI engines in edge cloud data centers. 
        • Tunnel multiple protocols such as PCIe, MIPI CSI-2, GMSL, field buses like Ethercat or Profinet via virtual connections over high-speed TSN.
        • Virtualize PLCs to run on datacenter infrastructure with advantages like virtualization, containerization, redundancy, backup organization etc. and without any compromises concerning real-time and high-speed requirements.
        • Use all advantages imaginable by having a high speed time sensitive network through the whole production plant.
      Robo/TSN - FPGA-based Industrial Network with TSN Architecture

      Robo/TSN for Industrial Network with Multi-Gigabit Ethernet & Multi Protocols

      AI and videos need high data rates and are breaking industrial networking. In industrial environments and control technology, real time requirements are common practice. Since camera technology, image recognition or AI become more and more usual, hard real time requirements combine with extremely high data rates. Sensors provide up to 25 Gbps data which has to be transferred, processed and evaluated real time with reliable low latency.

      MLE’s backbone-oriented approach allows it to tunnel modern multi-Gig sensor data (GigEVision, PCIe, MIPI CSI-2, GMSL, …) as well as industrial protocols like Ethercat or Profinet. Robo/TSN builds on patented and patent pending technology from MLE (US Patent Nos. 9,209,828 10,708,199 10,848,442 11,356,388 11,695,708, other Patents Pending).

      Robo/TSN - FPGA-based Industrial Network with TSN to Tunnel Multiple Protocols
      Application Example: Bridging of PCI Express connection through High Speed Ethernet TSN via Robo/TSN Packetizer/Depacketizer Devices
      Product Availability Matrix by FPGA Vendors
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      Features and Benefits

        • Bridging/ Tunneling of several protocols like PCIe, Ethercat, Profinet, Ethernet, CAN, etc.
        • Scalable from 1 to 100 Gbps 
        • Precision time synchronization with IEEE TSN or IEEE 1588 v2 (CERN White Rabbit)
        • Hardware accelerated deterministic transport with Ultra Low Latency (RTT < 600 ns)
        • Reliable transports via TCP/IP and/or Quad-RP/IP
        • Optional security features MACsec, IPSec, TLS

      Real-time Compliance

      Time Sync IEEE 802.1AS (IEEE 1588 profile)

      • Bounded Low Latency
        • IEEE 802.1Qav Credit Based Traffic Shaper
        • IEEE 802.1Qbu / 802.3br Preemption
        • IEEE 802.1Qbv Scheduled Traffic
        • IEEE 802.1Qcr Async Traffic Shaping
      • Reliability: IEEE 802.1Qca Path Control
        • IEEE 802.1CB Frame Replication & Elim.
      • Dedicated Resources & API
        • IEEE 802.1Qcc TSN Configuration
        • IEEE 802.1Qat Stream Reservation
        • IEEE 802.1CS Link-Local Reservation

      Robo/TSN Module for Industrial Network

      MLE NPAC for FPGA-based Robo/TSN IP, SmartNIC
      • Linux device drivers (GPL sources)
      • Application-specific expert design service 
      • Appliance implementation
      • License for ASIC/ FPGA Full System Stack
      • Pre-configured SmartNIC PCIe-Card, ready-to-run
      Datasheet
      Product Availability Matrix by FPGA Vendors
      Inquire Now
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      Fraunhofer Heinrich-Hertz Institute

      Founded in 1949, the German Fraunhofer-Gesellschaft undertakes applied research of direct utility to private and public enterprise and of wide benefit to society. With a workforce of over 23,000, the Fraunhofer-Gesellschaft is Europe’s biggest organization for applied research, and currently operates a total of 67 institutes and research units. The organization’s core task is to carry out research of practical utility in close cooperation with its customers from industry and the public sector.
      Fraunhofer HHI was founded in 1928 as “Heinrich-Hertz-Institut für Schwingungs- forschung“ and joined in 2003 the Fraunhofer-Gesellschaft as the “Fraunhofer Institute for Telecommunications, Heinrich-Hertz-Institut„. Today it is the leading research institute for networking and telecommunications technology, “Driving the Gigabit Society” .

       

      Fraunhofer Institute for Photonic Microsystems

      Fraunhofer IPMS is a worldwide leader in research and development services for electronic and photonic microsystems in the fields of Smart Industrial Solutions, Medical & Health applications and Improved Quality of Life. Innovative products can be found in all large markets – such as ICT, consumer products, automobile technology, semiconductor technology, measurement and medical technology – products which are based upon various technology developed at Fraunhofer IPMS.

      Data Diodes

      Data Diodes

      Data Diodes

      Data Diodes - Unidirectional Security Gateway

      A data diode or unidirectional network bridge / unidirectional security gateway is a piece of hardware used to connect two separated networks with the purpose to allow data to travel only in one direction, specifically, from one network into another. Applications are found in high security environments where they connect two or more networks of differing security classifications while making it physically impossible to transfer data in the direction from the lower to the higher security classification.

      Data Diodes Application - Example System Protection

      For this, MLE has partnered with Fraunhofer HHI to provide the industry-proven TCP/UDP/IP Network Protocol Acceleration Platform (NPAP) in form of NPAC, a PCIe Network Protocol Accelerator Card with quad-port 10G Ethernet. NPAC-40G implements reliable high-bandwidth low-latency TCP/UDP/IP transport plus Linux PCIe stream device drivers and can run customizable In-Network Processing such as red/ black network separation functionality on the integrated FPGA subsystem.

      Features and Benefits of Data Diodes

      • FHHL PCIe Card, PCIe 3.1 x8
      • 4x SFP+ for 10 Gig Ethernet
      • Intel Stratix 10 GX 400 FPGA, hardened
      • Tx-only and Rx-only (data-diode) network paths disconnect at PCB level or at circuit level
      • Optional TCP/IP Tx-only or Rx-only (FPGA-integrated TCP endpoint)
      • Optional In-Network Processing for Deep Packet Inspection and/or Firewall
      • Optional access logging
      • Customizable, Ready-to-Run

      Applications

      • Sending status Information from sensitive industrial plants
      • Sending video streams from sensitive video equipment / cameras
      • Protect classified data in high security networks and prevent it from leaking to low security networks, e.g. in defense
      • Critical Infrastructure and Industrial Internet of Things (IIoT)
        • Power plants and nuclear power plants
        • Power and water utilities and providers
        • Oil and gas deployments
        • Transportation, rail and air
      • Intelligence & Defense
        • Data Center
        • Tactical and removable media solutions
      • Commercial
        • Financial services
        • Manufacturing
        • Cloud services
        • Telecommunications providers
        • Security Information and Event Management logs
        • Intrusion Detection logs

      Availability

      MLE Data Diodes are available as a licensable full system stack or delivered as an integrated hardware/firmware/software solution in form of customizable FPGA-based Network Interface Cards (NIC) or as FPGA-based appliances.

      Data Diodes Solution - network interface card (NIC)

      Deliverables include:

      • Pre-configured PCIe Card, ready-to-run
      • Linux device drivers (GPL sources)
      • Application-specific expert design service (optional)
      • Appliance implementation (optional)
      Inquire Now

      Documentation

      Auto/TSN

      Auto/TSN

      In-Vehicle Network - Auto/TSN

      Auto/TSN stands for automotive data over Time-Sensitive Networks which is an in-vehicle network infrastructure based on open standards such as IEEE Ethernet. Auto/TSN is the results of a collaborative effort between MLE and MLE partners, Fraunhofer HHI and Fraunhofer IPMS.

      Fundamentally, Auto/TSN virtualizes the in-vehicle network infrastructure: Key objective is to reduce costs, increase scalability and enable upgradability for next-generation automotive architectures including electric and/or autonomous vehicles.

      in-vehicle network

      By tunneling sensor data along with PCIe and NVMe over Real-Time Multi-Gigabit Automotive Ethernet Auto/TSN simplifies the wire harness and enables more centralized architectures with higher levels of hardware / software integration. By offering PCIe as a common interface (for sensor-to-CPU and CPU-to-CPU connectivity) Auto/TSN different semiconductor SoCs become interchangeable. This significantly reduces semiconductor dependencies and infrastructure costs at the same time.

      Auto/TSN is highly scalable and supports line-rates up to 50 Gbps in FPGA and 100 Gbps in ASIC. Based on IPv4, the space for addressing nodes is 32 bits wide. The small hardware footprint allows zonal gateways with many ports.

      Auto/TSN is “software-defined” and builds from open standards such as IEEE 802.1Q TSN, IEEE 802.3 Ethernet, IETF TCP/IP, MIPI CSI-2, PCIe 4.0 and NVMe 1.4 and open-source Linux which eases hardware / software / system upgradability.

      Features & Benefits of In-Vehicle Network Auto/TSN

      Auto/TSN is a network infrastructure with a system/software focus which reduces the complexity of connecting sensors and centralized computers because it follows de-facto standards of open source network APIs such as RDMA, Linux netdev or SOME/IP.

      Benefits include:

      • Significant cost-down for in-vehicle networking and wire harnesses
      • Digital circuit implementation for zero CPU load
      • Deterministic and very low transport latencies, typ. within 5 micro-seconds
      • Low footprint enables ASIC or FPGA implementation

      The current implementation of TSN supports time-synchronization (IEEE 802.1AS) with 20 nanosecond precision, traffic shaping (IEEE 802.1Qav, 802.1Qbv), frame replication (IEEE 802.1CB) and stream prioritization (IEEE 802.1Qat) for high reliability, low-cost redundancy for functional safety and real-time behavior. Because for PCIe “best effort” is not sufficient, Auto/TSN implements a reliable transport on top of TSN which is compliant to IETF TCP/IP.

      For in-vehicle network security Auto/TSN can be complemented with state-of-the-art IEEE 802.1AE MAC Security Entities (MACsec) and/or IETF RFC 6071 Internet Protocol Security (IPsec) and/or IETF RFC8446 Transport Layer Security (TLS).

      Various Connectivity Schemes are supported:

      • Single CPU (PCIe Root-Port) to multiple devices (PCIe Endpoints)
      • Single CPU to multiple SSDs via NVM Express (NVMe)
      • Multiple CPUIs to multiple NVMe SSDs (via NVMe proxy)
      • Multiple CPUs to multiple CPUs via Inter-System Bridge (a.k.a. PCIe NTB)
      • Asymmetric sensor connectivity, e.g. MIPI CSI-2 to PCIe
      • IEEE 1722 style video transport
      in-vehicle network - Auto/TSN over 10G/25G/50G Ethernet

      Data-in-motion processing runs on dedicated on-chip full accelerators and frees up the CPUs from protocol handling. Our patented and patent-pending Heterogeneous Packet-Based Transport mechanism packetizes and de-packetizes PCIe, MIPI CSI-2 and other packet-based protocols and features low protocol overhead for high bandwidth and low and deterministic micro-second transport latency.

      PCIe Over Auto/TSN

      Auto/TSN implements a PCIe switch compliant with PCI-SIG Base Specification 3.0 (or newer) and NVM Express Specification 1.2 (or newer).

      PCIe Inter-System-Bridge for Auto/TSN

      Integrated PCIe Inter-System Bridges (a.k.a Non Transparent Bridges / NTB) enable CPU-to-CPU connectivity. The PCIe Inter-System Bridges use a least-cost write-only protocol to deliver very high read/write performance. This allows direct connectivity between sensors and multiple CPUs, GPUs, FPGA, SoCs, peripherals and next-generation storage within the entire vehicle.

      MIPI CSI-2 Over Auto/TSN

      Image sensors can connect via standard MIPI D-PHY and MIPI CSI-2, or else. Multicast functionality transports data from each image sensor to one, or more, central compute units under real-time conditions. Hence, Auto/TSN allows symmetric (e.g. PCIe-to-PCIe) and asymmetric (e.g. MIPI CSI-2-to-PCIe) communication schemes.​

      IEEE 1722 Video Transport Over Auto/TSN

      Complementing the MIPI CSI-2 over Auto/TSN transport, MLE has also implemented a solution that follows the Raw Video PDU Format from IEEE 1722.Similarly, this IEEE 1722 Raw PDU Transport supports point-to-point connectivity or multicast where one sensor's image data can be sent to multiple CPUs simultaneously.

      Availability

      Auto/TSN is available as a licensable integrated subsystem stack comprising digital circuit implementations and device driver software. This business model gives OEMs and Tier1s full control over how to integrate, either as a dedicated semiconductor component, or as modular function blocks inside a custom System-on-Chip with additional customer-specified functionality.

      MLE has been working with key semiconductor partners to deliver FPGA and ASIC based implementations of Auto/TSN ready for design and for production. Our early access program supports OEMs and Tier1s to perform in-house benchmarking and validation of Auto/TSN.

      Current implementations support gateway nodes with PCIe 3.0 and NVMe 1.2 with up to 4 lanes and with 5 or 8 GT/s, MIPI D-PHY 2.0 with up to 4 lanes and 2 Gbps and MIPI CSI-2 2.0 and up to 8 1G/10G Ethernet ports over copper or over fiber. “Lab Cars” based on professional 3rd party ASIC hardware emulators are available upon request.

      in-vehicle network - labcar

      Documentation

      Fraunhofer Heinrich-Hertz Institute

      Founded in 1949, the German Fraunhofer-Gesellschaft undertakes applied research of direct utility to private and public enterprise and of wide benefit to society. With a workforce of over 23,000, the Fraunhofer-Gesellschaft is Europe’s biggest organization for applied research, and currently operates a total of 67 institutes and research units. The organization’s core task is to carry out research of practical utility in close cooperation with its customers from industry and the public sector.
      Fraunhofer HHI was founded in 1928 as “Heinrich-Hertz-Institut für Schwingungs- forschung“ and joined in 2003 the Fraunhofer-Gesellschaft as the “Fraunhofer Institute for Telecommunications, Heinrich-Hertz-Institut„. Today it is the leading research institute for networking and telecommunications technology, “Driving the Gigabit Society” .

       

      Fraunhofer Institute for Photonic Microsystems

      Fraunhofer IPMS is a worldwide leader in research and development services for electronic and photonic microsystems in the fields of Smart Industrial Solutions, Medical & Health applications and Improved Quality of Life. Innovative products can be found in all large markets – such as ICT, consumer products, automobile technology, semiconductor technology, measurement and medical technology – products which are based upon various technology developed at Fraunhofer IPMS.

      Security & Trust

      OP-TEE Security & Trust

      OP-TEE: Open-Source Secure Operating System

      OP-TEE: Open Portable Trusted Execution Environment OP-TEE is a small secure operating system which, after authentication and decryption, gets loaded in an secured area in the memory. A Rich OS (e. g. Xilinx PetaLinunx) driver can request, via a Secure Monitor Call, the execution of a trusted application.

      OP-TEE is an Open-Source initiative driven by a Linaro team who maintains the code and makes it available for download at GitHub.

      MLE took the effort to port OP-TEE to Xilinx Zynq UltraScale+ MPSoC and RFSoC devices and included device specific optimizations. The outcome is two-fold: Tightly integrated Open-Source maintained by experts of Xilinx System-on-Chip and ACAP technology. And, additional professional services for customization and product life cycle support.

      Key Features of OP-TEE in FPGAs

      • Enables running secure & trusted applications from within a rich Linux operating system
      • Utilizes standard ARM Trusted Execution Environment (TEE)
      • Utilizes advanced security functions in Xilinx Zynq UltraScale+ MPSoC and RFSoC devices
      • Optional hardware acceleration for AES-CGM, RSA, SHA3, etc
      • Optional secure key handling with integrated PUF (Physically Unclonable Function) support
      • Optional handling for integrated eFUSE burning
      • Secure and non-secure bitstream loading
      • Support for custom secure functions in Programmable Logic

      Applications

      • Secure data storage
      • Secure communication
      • Secure Over-the-Air (SOTA) updates
      • Key to meet compliance with standards such as IEC 62443, IEC 27001 etc
      • Protect Functional Safety (SIL, ASIL) related designs
      • Secure touch inputs
      • Secure key handling

      Pricing

      MLE OP-TEE is available as pure Open-Source or as a professionally maintained source code deliverable:

      Product Name Deliverables Pricing
      OP-TEE Open-Source Edition (OP-TEE Free) Licensed under BSD / Linaro terms and available for download from GitHub. Free of charge
      Download Now
      OP-TEE Professional Edition (OP-TEE PRO) MLE Single-Site or Multi-Site Source Code License. Delivered by MLE in electronic form. Annual subscription fees starting at $42,800.-
      Application / Project specific Expert Design Services System-level design, modeling, implementation and test for realizing Domain-Specific Secure appplications. $1,880.- per engineering day (or fixed price project fee)

      OP-TEE Free

      (Open Source Edition)

      The OP-TEE Open Source Edition for Zynq UltraScale+ MPSoC and RFSoC is licensed under Linaro / BSD license as Open Source and comes with all source code and necessary packages. This version is ideal to explore the TEE world and develop your own trusted application. 

      Key Features and Benefits:

      • Open Source and Free of Charge
      • Runs in external PS-attached DDR memory
      • No Hardware acceleration for AES, RSA, SHA3
      • No access to PUF

      OP-TEE PRO

      (Professional Edition)

      MLE OP-TEE PRO can be licensed from MLE and will provide all source code and necessary packages to run OP-TEE on Zynq UltraScale+ MPSoC and RFSoC.

      Key Features and Benefits:

      • Hardware acceleration for AES
      • Hardware acceleration for RSA
      • Hardware acceleration for SHA3
      • With secure boot: access to PUF (Physical Uncloneable Function) functionality
      • Can load OP-TEE into TCM
      Product Availability Matrix by FPGA Vendors
      Inquire Now

      Comparison Between OP-TEE Free And OP-TEE PRO

      Functionality Supported

      OP-TEE Free

      OP-TEE PRO

      OP-TEE Basic functionality
      Trusted Applications with your own secure application
      Secure Paging (Hashed DDR Memory)
      Testsuite (10k+ Test Cases for selftest)

      (extended)

      AES-GCM (Xilinx CSU hardware accelerated)
      RSA (Xilinx CSU hardware accelerated)
      SHA3 (Xilinx CSU hardware accelerated)
      Secure Key handling with Physical Unclonable Function (PUF)
      Support for eFuse burning
      Secure/Nonsecure Bitstream Loading
      Performance Measurement of context switch or Trusted Application
      Custom Secure PL Functions
      Inquire
      Inquire

      Documentation

      Edit Template

      Frequently Asked Questions

      Most of the Zynq UltraScale+ MPSoC / RFSoC (ZynqMP) specific code for OP-TEE is currently going upstream to become part of the free open-source edition.

      However, there are functions of ZynqMP which require special handling, like the one-time-programmable eFuses, or support for custom secure PL functions, for example. Such device and/or application specific security functions of ZynqMP will be covered only by the PRO edition. Please refer to the comparison table above.

      Yes, MLE ships source code for OP-TEE PRO. Those ZynqMP platform specific code portions are available today and have passed review by the Xilinx Security Center of Excellence (COE). The most recent review was November 2019.

      OP-TEE Free is free-of-charge open-source software (FOSS) and can be downloaded from here: https://github.com/OP-TEE/ under a BSD 2-Clause License.

      Please refer to the Pricing section above.

      Function Accelerators

      Network Function Accelerators, FACs, NICs and SmartNICs

      NICs, SmartNICs, and Function Accelerator Cards with Network Accelerator

      A Network Interface Card (NIC) is a component that connects computers via networks, these days mostly via IEEE Ethernet – but what makes a NIC a SmartNIC? How can FPGA Network Accelerator make it operate more efficiently and enhance its performance to deliver deterministic networking?

      Performance gap between server CPU and the increasing computational demand of faster network port speeds over the past 40 yearsWith the push for Software-Defined Networking, (mostly open source) software running on standard server CPUs became a more flexible and cost-effective alternative to custom networking silicon and appliances. However, in the post Dennard scaling area, server CPU performance improvements cannot keep up with increasing computational demand of faster network port speeds.

      This widening performance gap creates the need for so-called SmartNICs. SmartNIC not only implement Domain-Specific Architecture for network processing but also offload host CPUs from running portions of the network processing stack and, thereby, free up CPU cores to run the “real” application.

      According to Gartner, Function Accelerator Cards (FACs) incorporate functions on the NIC that would have been done on dedicated network appliances. Hence, all FACs are essentially NICs, but not all NICs/SmartNICs are FACs. When deployed properly, FACs can increase bandwidth performance, can reduce transport latencies and can improve compute efficiency, which translates to less energy consumption.

      Deterministic Networking - Functional Accelerator Cards (FACs) - Landscape
      MLE has partnered with FPGA vendors, Fraunhofer Institutes and EMS partners to implement the FPGA Network Accelerator on FPGA-based FACs which deliver cost-efficient solutions for ultra-reliable, low-latency, deterministic networking.

      Features of FPGA Network Accelerator

      Ultra-Reliable, Low-Latency, Deterministic Networking

      With ultra-reliable, low-latency, deterministic networking we have borrowed a concept from 5G wireless communication (5G URLLC) and have applied this to LAN (Local Area Network) and WAN (Wide Area Network) wired communication:

      • Ultra-Reliable means no packets get lost in transport
      • Low-Latency means that packets get processed by a FAC at a fraction of CPU processing times
      • Deterministic means that there is an upper bound for transport and for processing latency

      We do this by combining the TCP protocol, fully accelerated (in FPGA or ASIC using NPAP), with TSN (Time Sensitive Networking) optimized for stream processing at data rates of 10/25/50/100 Gbps. These so-called TCP-TSN-Cores, the FPGA network accelerator, not only give us precise time synchronization but also traffic shaping, traffic scheduling and stream reservation with priorities.

      We believe that FPGAs are very well positioned as programmable compute engines for network processing because FPGAs can implement “stream processing” more efficiently than CPUs or GPUs can do. In particular, when the networking data stays local to the FPGA fabric Data-in-Motion processing can be done within 100s of clock cycles (which is 100s of nano-seconds) and can be sent back a few 100 clock cycles later, an aspect with is referred to as Full-Accelerated In-Network Compute.

      While FPGA technology has been on the forefront of Moore’s Law and modern devices such as AMD/Xilinx Versal Prime or Intel Agilex or Achronix Speedster7t can hold millions of gates, FPGA processing resources must be used wisely, when Bill-of-Materials costs are important. Therefore, at MLE we have put together a unique combination of FPGA and open-source software to achieve best-in-class performance while addressing cost metrics more in-line with CPU-based SmartNICs.

      Unique and Cost-Efficient Combination of Open Source

      The Open Source Technologies We Borrow From

      Linux kernel​

      Meanwhile highly optimized for networking​

      OpenvSwitch

      An open source multi-layer network switch​

      Corundum

      A vendor-neutral open-source high-performance FPGA-based NIC

      SONiC

      Software for Opensource Networking in the Cloud​​

      Dataplane Development Kit

      DPDK​

      Intel Compiler for SystemC​​

      An open source High-Level Synthesis engine​​

      OpenNIC

      The GitHub project focusing on AMD/Xilinx Alveo cards​

      Xilinx Vitis HLS LLVM

      The High-Level Synthesis Frontend for Xilinx FPGAs

      High-Level Synthesis plays a vital role in our implementation as it allows MLE and MLE customers to turn algorithms implemented in C/C++/SystemC into efficient FPGA logic which is portable between different FPGA vendors.

      To build a high-performance FAC platform, portions of the above have been integrated together with proven 3rd party networking technologies:

      Corundum In-Network Compute + TCP Full Accelerator

      Corundum is an open-source FPGA-based NIC which features a high-performance datapath between multiple 10/25/50/100 Gigabit Ethernet ports and the PCIe link to the host CPU. Corundum has several unique architectural features: For example, transmit, receive, completion, and event queue states are stored efficiently in block RAM or ultra RAM, enabling support for thousands of individually-controllable queues.

      Corundum In-Network Compute with FPGA Network Accelerator (TCP Full Accelerator)MLE is a contributor to the Corundum project. Please visit our Developer Zone for services and downloads for Corundum full system stacks pre-built for various in-house and off-the-shelf FPGA boards.

      MLE combines the Corundum NIC with NPAP, the TCP/UDP/IP Full Accelerator from Fraunhofer HHI, via a so-called TCP Bypass which minimizes processing latency of network packets: Each packet gets processed in parallel by the Corundum NIC and by NPAP. The moment it can be determined that the packet shall be handled by NPAP (based on IP address and port number) this packet gets invalidated inside the Corundum NIC. If a packet shall not be processed by NPAP, it get’s dropped in NPAP and will solely be processed by the Corundum NIC.

      Fundamentally, this implements network protocol processing in multiple stages: Network data which is latency sensitive does get processed using full acceleration, while all other network traffic is handled either by a companion CPU and/or by the host CPU.

      Applications of FPGA Network Accelerator

      MLE’s Network Accelerators are of particular value where network bandwidth and latency constraints are key:

      • Wired and Wireless Networking
      • Acceleration of Software-Defined Wide Area Networks (SD-WAN)
        • Video Conferencing
        • Online Gaming
        • Industrial Internet-of-Things (IIoT)
      • Handling of Application Oriented Network Services
      • Mobile 5G User-Plane Function Acceleration
      • Mobile 5G URLLC Core Network Processing with TSN
      • Offloading OpenvSwitch (OvS), vRouter, etc

      Key Benefits

      The following shows the key benefits of MLE’s technology by comparing open-source SD-WAN switching in native CPU software mode against MLE’s FPGA Network Accelerator:

      Bandwidth Comparison between SD-WAN in native CPU software mode and with MLE FPGA Network Accelerator
      Latency Comparison between SD-WAN switching in native CPU software mode and with MLE's FPGA Network Accelerator

      Compared with plain CPU software processing MLE’s Ultra-Reliable Low-Latency Deterministic Networking increases network bandwidth and throughput close to Ethernet line rates, in particular for smaller packets, which reduces the need for over-provisioning within the backbone. And, processing latencies can be shortened significantly which is important, for example, when delivering a lively audio/video conferencing experience over WAN.

      Availability

      MLE’s FPGA Network Accelerator is available as a licensable full system stack and delivered as an integrated hardware/firmware/software solution. In close collaboration with partners in the FPGA ecosystem, MLE has ported and tested variations of the stack on a growing list of FPGA cards. Currently, this list comprises high-performance 3rd party hardware as well as MLE-designed cost-optimized hardware:

      FPGA Card

      Hardware Description & Features

      Status

      Verified modules of MLE FPGA Network Accelerator - NPAC-Ketch, MLE-designed single-slot FHHL PCIe card

      NPAC-Ketch, MLE-designed single-slot FHHL PCIe card

      • Cost-optimized Intel Stratix 10 GX 400 FPGA
      • Optional 4 GB DDR4 SO-DIMM attached to Programmable-Logic
      • 4x SFP+ (4x 10 GigE)PCIe 3.1 8 GT/sec x8 lanes
      • 50 Watts TDP passive cooling front-to-back
      		Available
      Inquire
      Verified modules of MLE FPGA Network Accelerator - AMD/Xilinx Alveo U280

      Alveo U280, AMD/Xilinx-designed dual-slot FHFL PCIe card

      • AMD/Xilinx UltraScale+ FPGA
      • 32 GB DDR4 DRAM plus 8 GB HBM2 DRAM
      • 2x QSFP28 (2x 100 GigE or 4x 25 GigE or 8x 10 GigE)
      • PCIe 4.0 16 GT/sec x8 lanes
      • 225 Watts TDP active cooling

      Early Access

      Inquire

      Verified modules of MLE FPGA Network Accelerator - Intel N6000-PL

      N6000-PL, Intel-designed single-slot FHHL PCIe card

      • Intel Agilex AGF014 F Series FPGA
      • 4x 4 GB DDR4 SO-DIMM attached to Programmable-Logic
      • 2x QSFP28 (2x 100 GigE or 4x 25 GigE or 8x 10 GigE)
      • PCIe 4.0 16 GT/sec x16 lanes
      • ARM A53 Quad-Core CPU with 1 GB DDR4 DRAM running Linux
      • 125 Watts TDP passive cooling

      Early Access

      Inquire

      Documentation

      Solutions

      Network Acceleration and Security Solutions

      Solutions

      FPGA-Based Accelerator and Security Solutions

      To meet the growing demands of modern systems for higher data throughputs, lower processing latencies and heightened security, MLE leverages FPGAs to accelerate software-rich system stacks and protocols. Our solutions typically ship as FPGA Full System Stacks comprising software (based on Linux), hardware (based on vetted 3rd party FPGA boards), and FPGA design projects.

      Automotive

      FPGA solutions for smart vehicle - Automotive, Truck, Bus

      Modern Zone-based automotive architectures require high data rates and real-time behavior at the same time. MLE solutions include stacks and subsystems for in-vehicle networking, and prototyping systems for efficient development and testing.

      Auto/TSN In-Vehicle Networks
      Auto/RPS - Zonal Gateway /ECU Prototyping
      Long-Range Tunnel for ADAS Sensors

      Industrial & Robotics

      FPGA solutions for industrial robots

      Generative AI and high data rate machine vision push bandwidth demands for real-time industrial networks beyond 10 Gbps. MLE solution include SmartNICs and access points for low-latency, low-jitter real-time networking, and for virtualizing PLCs.

      Robo/TSN Industrial Networking
      Long-Range-Tunnel for Machine Vision
      Industrial Connectivity Prototyping

      Wired & Wireless Communication

      MLE provides FPGA Function Accelerator Cards and SmartNICs for wired and wireless communications. A unique combination of technology from Fraunhofer HHI plus MLE’s patented and patent-pending Full Accelerators accelerates Software-Defined Networking (SDN) and SD-WAN.

      FPGA Function Accelerator Cards
      SDN and SD-WAN Accelerators
      TCP/UDP/IP Network Protocol Accelerator Platform
      FPGA SmartNIC with TCP/UDP/IP Acceleration

      Storage Solutions

       

      Next-generation storage protocols such as NVMExpress (NVMe) provide significant performance benefits and, when combined with FPGAs, can be used as storage acceleration IP cores for Computational Storage, Data-in-Motion processing and high-speed data capture and recording.

      100/200/400G NVMe FPGA RAID
      PCIe 3.0/4.0/5.0 NVMe Streamer
      High-Speed Data Recording
      High-Speed NVMe Streaming
      Key-Value-Store (KVS) Accelerator for Data Center Storage

      Test & Measurement

      MLE has been working with 3rd party system companies to deliver reliable, customizable turnkey solutions for high-speed data acquisition, recording and replay, as they often are needed in Test & Measurement systems for automotive, aerospace, defense, industrial, etc.

      100/200/400G NVMe FPGA RAID
      High-Speed Data Recording
      High-Speed NVMe Streaming

      Security and Trust

      MLE provides solutions to secure products based on FPGA technology: MLE has ported OP-TEE to AMD/Xilinx Zynq UltraScale+ MPSoC and RFSoC including support for black keys, PUFs, eFUSES, etc. Furthermore, MLE has introduced networking security products for deep packet inspection and Data Diodes.

      Smart Data Diodes
      OP-TEE Trusted Execution for AMD/Xilinx