PCI Express over IP, Accelerated – A Low Latency Fabric for System-of-Systems
![PCIe IP - PCI Express over IP Architecture](https://www.missinglinkelectronics.com/wp-content/uploads/2019/06/pcie-over-xxx.jpg)
Presentation at Session 18/II of the Embedded World Conference 2016 in Nuremberg
FPGA-based full accelerators enable reliable tunneling of PCI Express of existing LAN. This approach is transparent to the CPU Root Complex and Operating System and can be scaled to match 1/10/25/40 GigE line rates.