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      CORUNDUM Project Releases AMD/Xilinx Zynq MPSoC Support

      CORUNDUM, the open source In-Network Compute Platform hosted on Github now supports the integrated ARM A53 Processing System of AMD/Xilinx Zynq UltraScale+ MPSoC FPGA. Based on key contributions from MLE this work allows implementing complete Linux subsystems running within the SmartNIC, separate and independent from the underlying host operating system. Work was tested using the Sidewinder-100 card from Fidus Systems, a fellow AMD/Xilinx Alliance member.

      MLE Integrates CORUNDUM MQNIC Support into DPDK

      MLE has integrated support for the CORUNDUM project’s MQNIC into the open source Data Plane Development Kit. MQNIC is the open source network interface card within CORUNDUM, the open source FPGA-based In-Network Compute Platform. DPDK now has support for a single interface and a single port per interface of MQNIC. MLE work was tested with a 10G version of MQNIC build for the Fidus Sidewinder-100 board which features an AMD/Xilinx Zynq UltraScale+ MPSoC ZU19EG.

      Fraunhofer IPMS and MLE Present at Automotive Ethernet Congress, June 1-2, 2022

      At the Automotive Ethernet Congress 2022, on June 2nd we present "Zone-Based Automotive Backbone" a.k.a. Auto/TSN which is joint work between MLE and Fraunhofer IPMS on how to combine TSN Ethernet, TCP/IP as an ultra-reliable deterministic low-latency transport for tunneling PCIe and other protocols for long-reach. The joint presentation also features a lab car demo in which tunneling effects on bandwidth and latency within the network will be explained.

       

      NPAP RTL Simulation Demonstrates Low-Latency TCP/IP

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      MLE has complemented NPAP, the TCP/UDP/IP Full Accelerator from Fraunhofer HHI, with an RTL Simulation environment for Xilinx Vivado ISim and for the Questa Advanced Simulator from Siemens EDA. This simulation environment is available free-of-charge to all licensees of NPAP with an active maintenance subscription. For more information please read the MLE Technical Brief TB20220305 titled “Latency Measurement of 10G/25G/50G/100G TCP-Cores Using RTL Simulation”.

      Real-time Parallel Voice, Data and Video Streams in Defense System Solutions

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      Elbit Systems Deutschland is a vendor for mobile high performance communications and tactical data links. This allows parallel voice, data and video streams in real time. Furthermore, Elbit Systems Deutschland provides expertise for communication and reconnaissance technologies with ongoing engagement in security related systems which makes Elbit Systems Deutschland a reliable and competent partner in defense system solutions within the fields of radio communication, electro optics, protection systems, uncrewed systems up to complete cyber solutions.

      Since 2018 Elbit Systems Deutschland has been relying on Missing Link Electronics (MLE) for FPGA design services. MLE brings expertise in implementing various protocols like TCP/IP, I2C, SPI, I2S, and in line processing and system integration of timecode protocols like IRIG, HaveQuick and pulse-per-second, and deep knowledge in FPGA technology like AMD Spartan 7, AMD Zynq Ultrascale+ MPSoC and ARM based Microcontrollers.

      MLE has implemented application specific FPGA functionality and corresponding custom device drivers and included them into an up-to-date Yocto build flow. MLE has verified the design by tests and demonstrations on the target hardware platform.

      All tasks were delivered within time, budget and in close communication with the Elbit Systems Deutschland team which allowed alignment and efficient progress of both engineering teams.

      MLE & Intel PSG Optimize NPAP for Intel HyperFlex Architecture

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      As the outcome of joint engineering collaboration between Intel PSG and MLE Germany, an new version of NPAP, the TCP/UDP/IP Full Accelerator from Fraunhofer HHI was released by MLE. This release incorporates many code optimizations for utilizing the Intel HyperFlex technology. Intel HyperFlex FPGA Architecture addresses increased bandwidth demands via improved FPGA logic clocking. For a typical NPAP setup clock speed was improved by more than 1.5x to currently over 500 MHz. Because of NPAP's unique 128-bit wide datapath architecture, this enables more than 60 Gbps line rates. NPAP-100G for Intel Hyperflex is made available by MLE as a licensable subsystem stack or as a Function Accelerator Card based on Stratix 10GX devices.

       

      MLE Presents CORUNDUM In-Network Compute at FOSDEM’22

      At FOSDEM’22, an annual event to promote the widespread use of free and open source software, MLE co-presents an update of the CORUNDUM.io project. CORUNDUM is an open-source project hosted at Github for building high-performance FPGA-based Network-Interface Cards (NIC) or in-network compute platforms / SmartNICs. MLE’s work includes enhanced support for Xilinx Zynq UltraScale+ MPSoC, for example interfacing with Linux running on the ARM-based Processing System (PS). Read more on the work presented…