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      News

      News

      MLE continues to work with a wide range of partners to develop advanced FPGA-based networking and storage applications, as well as to share our experience and latest research results in seminars as well as webinars. Here we share our latest news and events.

      MLE Updates TCP/UDP/IP Network Protocol Accelerator Platform

      MLE Updates TCP/UDP/IP Network Protocol Accelerator Platform

      Apr 15, 20231 year ago

      MLE has updated NPAP, the Network Protocol Accelerator Platform based on Fraunhofer HHI’s TCP/UDP/IP stack for ASIC and FPGA. Work includes enhancements for performance and interoperability when connecting to Microsoft…

      MLE Presents at Embedded World 2023

      MLE Presents at Embedded World 2023

      Mar 14, 20231 year ago

      5G Radio addresses machine-type communication with low energy demands. 5G Edge Clouds reduce processing latency by bringing extra compute close to the “edge”. To be cost efficient, Edge Cloud systems…

      MLE Opens R&D Offices at Schindler Innovation Hub in Berlin

      MLE Opens R&D Offices at Schindler Innovation Hub in Berlin

      Mar 1, 20231 year ago

      Berlin has always been a hot-bed for research and development of new communication technologies. BMBF funded Project 6G-ICAS4Mobility along with the German Platform for Future Communication Technologies and 6G (6G…

      MLE Participates at AMD/Xilinx Security Working Group 2022

      MLE Participates at AMD/Xilinx Security Working Group 2022

      Dec 6, 20222 years ago

      The AMD-Xilinx Security Working Group takes place face-to-face in Munich, Germany, from December 6-7, 2022. Presentations include the latest security features in Versal ACAP and updates for the product roadmap.…

      MLE Joins Central Car Server Supercomputing Research for Automotive, Funded by German BMBF

      MLE Joins Central Car Server Supercomputing Research for Automotive, Funded by German BMBF

      Dec 1, 20222 years ago

      Advanced Driver-Assist Systems (ADAS) and Autonomous Vehicle (AV) functions require a challeging combination of of compute performance and energy efficiency, especially when deployed in Battery Electric Vehicles (BEV). MLE has…

      Intel Partner Alliance Gold Status Renewed

      Intel Partner Alliance Gold Status Renewed

      Dec 1, 20222 years ago

      Intel Corporation has renewed MLE’s Gold Status membership in the Intel Partner Alliance for 2023. The Intel Partner Alliance unifies all partners in a modern program that enables collaboration and…

      MLE’s Auto/TSN for Digital RADAR Networks Receives BMBF Funding

      MLE’s Auto/TSN for Digital RADAR Networks Receives BMBF Funding

      Dec 1, 20222 years ago

      In-Vehicle Networks of the future will be driven by the large bandwidth needs of modern sensors, in particular Radar (Radio Detection and Ranging), and more importantly networks of digital Radar…

      MLE exhibits at SC22

      MLE exhibits at SC22

      Nov 4, 20222 years ago

      Partner ProDesign and MLE will showcase High-Performance Compute solutions at Super Computing Conference SC22. To address the acceleration needs of Disaggregated Computational Storage, ElasticSearch, or At-Speed In-Network Processing the featured…

      MLE Joins German 6G Radio Initiative, Receives BMBF Funding

      MLE Joins German 6G Radio Initiative, Receives BMBF Funding

      Nov 1, 20222 years ago

      Integrated Communication and Sensing (ICAS) has become a key research topic for realizing next-generation mobility solutions. For 6G Radio, ICAS enables sensor systems to cooperate and to interact via 6G…

      MLE Presents at SNIA SDC 2022

      MLE Presents at SNIA SDC 2022

      Jul 21, 20222 years ago

      At SNIA Storage Developers Conference (SDC) 2022, on Sept. 14, MLE and partner Fraunhofer IPMS will present “Converging PCIe and TSN Ethernet for Composable Infrastructure in High-Performance In-Vehicle Embedded Systems”:…

      Success Stories

      Success Stories

      Over the last decade, MLE has gained deep experience working with clients and partners on FPGA-based subsystems for a wide range of applications, such as networking, storage, telecommunication, automotive, aerospace/defense, test & measurement, and video streaming. 

      Corundum DPDK Driver

      MLE presents an initial DPDK driver for the corundum multi-queue network interface card (mqnic). The driver is available via the respective github repository of Missing Link Electronics.

      DPDK is the acronym for Data Plane Development Toolkit and it consists of libraries to accelerate packet processing workloads running on a wide variety of CPU architectures. To enable packet reception and transmission, a driver is required to integrate various NICs into the DPDK.

      Corundum mqnic is a project aiming at providing a fully open source FPGA based in network compute platform, comprising Linux drivers and gateware supporting various FPGA vendors, families and devices.

      The Missing Link Electronics DPDK Driver for the Corundum mqnic now enables a fully open source development environment for high-performance network processing research. This may involve new hardware software partitioning as, for the first time, both the hardware and the software side are available as open source.

      The driver is available for multiple dpdk-stable versions 22.11, 21.11 and 20.11 and supports multiple interfaces per device. It has been tested against corundum version 0965c77 using a ZCU106 implementation featuring 2x 10 GbE interfaces and a custom Fidus Sidewinder-100 implementation featuring 8x 10G interfaces. The tests are based on the DPDK forwarding example and an iperf client and server running on two additional machines, connected to one of the network interfaces implemented by corundum, each.

      Berlin 6G Conference 2023

      Berlin 6G Conference is the annual networking event of the German 6G Program, organized by the 6G Platform Germany, will take place at the Berlin Congress Center (BCC) from June 27-29, 2023.

      The 6G Platform Germany is an R&D initiative with a total funding of €700 million. One of the core topics is the combination of a secure radio and sensing, so-called Integrated Communication and Sensing (ICAS) with aims to develop such a combination for communication and sensing of the environment and to integrate it into a joint system for the future mobile radio standard 6G.

      MLE actively contributes to the 6G-ICAS4Mobility project.

      Trenz Electronic GmbH and Missing Link Electronics, Inc. Enter Strategic Partnership to Deliver Turnkey Solutions and Full System Stacks with FPGA

      Trenz Electronic GmbH (Trenz), Hüllhorst, Germany, and Missing Link Electronics, Inc. (MLE), San Jose, CA, both Premier Members of the AMD Adaptive Computing Partner Program, have entered a strategic partnership to provide FPGA-based Turnkey Solutions and Full System Stacks, extending their European collaboration to Canada and the United States. 

      The market for Field-Programmable Gate Arrays (FPGA) continues to grow significantly owing to its increasing performance, flexibility, cost and energy benefits in various end-use industries: Automotive, Aerospace/Defence, Industrial/Scientific/Medical, Compute, Wired and Wireless Telecommunication. However, the difficulty in programming FPGAs, in particular those System-on-Chip (SoC) FPGA with embedded CPUs, has long been considered a disadvantage that prevents FPGA from becoming a general computation solution. Integrated and pre-validated building blocks such as Trenz’ System-on-Modules (SoM) FPGA hardware and MLE’s Compute, Video, Storage and Networking FPGA software subsystems significantly increase the productivity of end-users of FPGAs while shortening time-to-market for new product initiatives.

      The aim of this strategic partnership is to de-risk and to cost-down High-Performance Compute and Embedded Systems by delivering complete FPGA Turnkey Solutions and Full System Stacks to end users in volume.

      Trenz and MLE have established close engineering collaboration and a track record of shipping integrated FPGA solutions based on Trenz SoM running MLE’s System Software Stacks with Compute, Video, Storage and/or Network Acceleration. Given MLE’s presence in the heart of Silicon Valley, this new level of partnership gives customers in the USA and Canada easy access to FPGA-based cards, boards, SoMs from Trenz along with IP Cores, design services and engineering support from MLE experts. 

      A 40 GigE SD-WAN Access Point and Customer Premise Equipment – which is now shipping to a green-field telco customer in Canada – is a typical example of this close partnership: To de-risk the project, MLE started with the AMD Zynq UltraScale+ MPSoC on the Trenz SoM TE0808 within a Trenz Starter Kit and could deliver a working Proof-of-Concept within weeks. Based on this success, MLE modified the Trenz carrierboard TEBF0808 to meet the customer’s connectivity requirements. Again, manufactured by Trenz Electronic Manufacturing Services (EMS), the first product shipped within less than a year. For volume ramp-up Trenz and MLE are planning a so-called chip-down solution (unifying the SoM with the baseboard to a single PCB) which maintains key system/software compatibility but shrinks the hardware Bill-of-Materials (BoM) costs. 

      About Trenz

      Since 1992 Trenz Electronic has operated as a provider of development and production services for the electronics industry. Services include design-in support as well as turnkey designs which typically covers all steps from product specification, hard- and software design up to prototyping and production. Trenz specializes in the design of high-speed data acquisition, high-accuracy measurement and embedded digital signal processing systems based on FPGA and CPU architectures. Trenz development service is supplemented by FPGA-and MCU-based development boards and tools.

      About MLE

      Head-quartered in Silicon Valley with engineering offices in Berlin and Neu-Ulm, Germany, Missing Link Electronics (MLE) has successfully delivered solutions for Wired and Wireless Telecommunications, Datacenter storage, network protocol and algorithm acceleration in the cloud, Autonomous Driving and ADAS and Image processing and sensor fusion with camera, Radar, Lidar sensors etc.

      Advantages of Using TCP for GigE Vision Devices

      Allied Vision Technologies GmbH in Stadtroda, Germany, has worked with Missing Link Electronics (MLE) to integrate and to optimize MLE NPAP, the TCP/UDP/IP Full Accelerator Stack from Fraunhofer HHI, into a series next-generation camera products. NPAP, the TCP/IP Full Accelerator from Fraunhofer HHI, provides TCP connectivity in accordance with the GigE Vision standard.

      For more than 30 years, Allied Vision Technologies GmbH has been helping people to reach their imaging goals. Allied Vision supplies camera technology and image capture solutions for industrial inspection, medical and scientific imaging, traffic monitoring, and many more application areas in digital imaging. With a deep understanding of customers’ needs, Allied Vision finds individual solutions for every application, a practice which has made Allied Vision one of the leading camera manufacturers worldwide in the machine vision market. The company has nine locations in Germany, Canada, the United States, Singapore, and China and is represented by a network of sales partners in over 30 countries.

      For more information about the Advantages of Using TCP for GigE Vision Devices please read this White Paper.

      Looking for FPGA-based Solutions for High-Speed GigE Cameras?

      MLE Updates TCP/UDP/IP Network Protocol Accelerator Platform

      MLE has updated NPAP, the Network Protocol Accelerator Platform based on Fraunhofer HHI’s TCP/UDP/IP stack for ASIC and FPGA. Work includes enhancements for performance and interoperability when connecting to Microsoft Windows 10 and Windows 11 TCP stacks. And, in close collaboration with Intel’s Programmable Solutions Group, NPAP was optimized for HyperFlex2 in new Agilex FPGAs. Intel HyperFlex and HyperFlex2 can significantly increase performance via Hyper-Retiming, Hyper-Pipelining and Hyper-Optimizations while avoiding “bloating” the FPGA design.