Berlin 6G Conference is the annual networking event of the German 6G Program, organized by the 6G Platform Germany, will take place at the Berlin Congress Center (BCC) from July 2-4, 2024.
The 6G Platform Germany is an R&D initiative with a total funding of €700 million. One of the core topics is the combination of a secure radio and sensing, so-called Integrated Communication and Sensing (ICAS) with aims to develop such a combination for communication and sensing of the environment and to integrate it into a joint system for the future mobile radio standard 6G.
MLE has been actively contributing to the 6G-ICAS4Mobility project in respect of high-accuracy networking technology with precision time synchronization.
Modern Systems can combine a lot of sensors like cameras, radars, Lidar or high speed ADC/DAC. During development, it is often required to record raw data. A FPGA Based High Speed Recorder can collect data from many different sources and can record them on non-volatile memory. Building a High Speed Data Recorder has many pitfalls which can cause the project to fail as a single flaw can have a heavy impact on performance.
This presentation will walk through our lessons learned from building such a recorder: starting by analyzing the data path, discussing the impact of data granularity and data width, different local buffer options such as DDR / HBM2 / UltraRAM / BRAM, characteristics of AXI4 / PCIe and also the limitations of most NVMe SSDs in the aspect of sustained writing performance. Then the presentation will end with an architectural overview of the final system and the achieved performance.
Date: Tuesday July 2th, 2024
Track 1 – Application (starts at 4:30pm CEST)
Location: Hotel NH München Ost Conference Center, Munich, Germany
Join us at FPGA Conference 2024 to learn more details about the high-speed 400GBit/s data recording technology!
White Rabbit is a technology that allows to synchronize networked devices or endpoints tens of kilometers apart with a sub-nanosecond accuracy. With minor, but incompatible changes, it is now fully integrated into the IEEE1588-2019 or PTP v2.1 standard as high accuracy (HA) profile.
Each endpoint employs frequency and phase measurement and adjustment techniques using field programmable gate arrays (FPGAs) and external voltage-controlled crystal oscillators (VCXOs). This usually requires external circuit boards with specific components not available on commercially off-the-shelf (COTS) development boards.
At the workshop, we will share our results of implementing White Rabbit nodes on multiple development boards, e.g. AMD ZC706 and ZCU102 by only using the FPGA’s resources such as either Mixed-Mode Clock Managers (MMCMs) on the ZC706 or Quad Phase-Locked-Loops (QPLL) on the ZCU102, capable of fully synchronizing with other White Rabbit hardware, such as a Seven Solutions White Rabbit switch (WRS 3/18).
We also compared our synchronized endpoints on the ZCU102 and ZC706 to the timing source of the White Rabbit switch. We obtained initial experimental results of our two VCXO-less White Rabbit implementations using a time interval counter (TIC) for measuring the generated pulse-per-second (PPS) signal and a custom Digital Dual Mixer Time Difference (D-DMTD) circuit for the 10 MHz signal. To validate our measurement approach, we also did a spectrum analysis and a time-interval error analysis of the 10 MHz signals with a professional Rohde&Schwarz RTO1044 oscilloscope.
This update is fixing minor issues with AXI4 bus scheduler fairness, IP Core packaging for AMD/Xilinx Versal FPGA as well as UDP only instantiations. All licensees who are on an active maintenance contract with MLE will have access to this update.
We suggest that customers who are in a late phase of an FPGA design project integrating MLE NPAP shall contact MLE to discuss risks and benefits when updating.
Our FPGA Full System Stacks have a particular focus on high-speed connectivity using PCI Express, MIPI CSI-2, GMSL, Multi-Gigabit Ethernet. We target applications which require reliable, low-latency, high-throughput network transports, high-speed data acquisition, augmented stereo computer vision, high-speed data record & replay. All those are driven by AI algorithms processing massive data from high-resolution cameras, Radar and Lidar sensors.
Please visit us to experience the featured solutions built on top of the latest Trenz SoMs:
We also invite you to join the Embedded World Conference where our engineers present FPGA technology for embedded networking acceleration for high-speed data streaming:
These days high-performance embedded systems operate highly interconnected. Within these networks the systems often transport data at high bandwidth or low-latency. While the system needs to serve the network performance needs, additional control tasks are to be performed. For the latter task usually a processing system runs a Linux or another real-time embedded operating system. Then the former, high-performance network data cannot be fully handled by the embedded processing system.
To overcome this situation, a network stack implemented in hardware, e.g. in an FPGA, can offload the processing subsystem. To simplify the system design and reduce cost, the number of physical networking interfaces can be reduced to one. This, on the other hand, requires an architecture that shares a single high-speed network interface across the processing system and the hardware network stack. Usually, embedded systems in addition require highly accurate time synchronization, usually provided via PTPv2.
The presentation shares the architecture options and results based on an implementation for a high-speed streaming data interface, both a source and a sink that shares a physical network interface with a open source network interface card implementation connected to a processing system. This NIC is operated by a Linux driver and allows for PTPv2 based time synchronization via a Linux daemon. The whole system is implemented into an AMD MPSoC.
Date: Thursday April 11th, 2024
Session 1.9 Internet of Things / Platform 2 (starts 2:30pm CEST)
Location: NCC Ost Convention Center, Nuremberg, Germany
Join us at EW24 Conference to learn about the latest time synchronization technology for high-speed data streaming!
Modern Systems can combine a lot of sensors like cameras, radars, Lidar or high speed ADC/DAC. During development, it is often required to record raw data. A FPGA Based High Speed Recorder can collect data from many different sources and can record them on non-volatile memory. Building a High Speed Data Recorder has many pitfalls which can cause the project to fail as a single flaw can have a heavy impact on performance.
This presentation will walk through our lessons learned from building such a recorder: starting by analyzing the data path, discussing the impact of data granularity and data width, different local buffer options such as DDR / HBM2 / UltraRAM / BRAM, characteristics of AXI4 / PCIe and also the limitations of most NVMe SSDs in the aspect of sustained writing performance. Then the presentation will end with an architectural overview of the final system and the achieved performance.
Embedded systems such as in-vehicle networks, modern factory automation or autonomous robots, for example, are undergoing a major shift: Enabled by high-resolution cameras, Radar and Lidar sensors, AI algorithms can implement smartness and ambient awareness, but for this need more compute power and higher bandwidth. Industrial and automotive networks must now transport many Gigabits per second, while guaranteeing reliable and secure data delivery, on-time.
TCP, the Transmission Control Protocol, was introduced half a century ago and is a good protocol used almost everywhere in wired or wireless, robotics, factories, vehicles. Unfortunately, TCP has some bad aspects: A significant computational burden. And some outright ugly: Unpredictable tail latency and head-of-line blocking, making real-time behavior difficult.
Our presentation shares quantitative analysis results and presents alternatives: For latency analysis we present benchmarks results from network simulation which show the significant tail latencies for TCP and the undesirable outcomes of TCP’s “not-so-fair” scheduling.
As an alternative we present the Homa protocol from Stanford University. Instead of stream-based connections, Homa is message based and connectionless, which caters better to the needs of modern distributed, microserviced, virtualized embedded architectures. Homa provides significant advantages over TCP when it comes to tail latency and infrastructure efficiency in real-life networks.
With the new Encrypted Network Accelerator Solutions brought to the market, Xiphera and MLE offer a cryptographically secure and reliable connection between devices over TCP/IP.
Xiphera, Ltd, designing hardware-based security solutions using standardised cryptographic algorithms, and Missing Link Electronics (MLE) with expertise in offloading CPUs and accelerating software-rich system stacks via so-called Domain-Specific Architectures, announce a partnership to introduce Encrypted Network Accelerator Solutions (ENAS). With the joint solutions brought to the market, Xiphera and MLE offer a cryptographically secure and reliable connection between devices over TCP/IP.
The ENAS solutions combine MLE’s highly modular TCP/UDP/IP Network Protocol Accelerator Platform (NPAP) with Xiphera’s TLS 1.3 security protocol solution. While accelerating the device network up to 10/25/50 GigE, it implements Transport Layer Security (TLS), a cryptographic security protocol providing end-to-end data security, on top of the MLE’s Transmission Control Protocol (TCP) layer for more secure and accelerated network communication. The solution is delivered as an IP core for FPGA circuits.
The Encrypted Network Accelerator Solutions are best suited for applications where the highest security level and high-speed data transmission are required, such as critical communications in defense, space technology, and energy production and distribution. Since the TCP/IP stack and the TLS 1.3 security protocol – including importantly both key exchange and key management – are both executed entirely in hardware, the joint solution has both scalable high-speed performance and minimised attack surface, especially when compared to a software-based approach.
“As mission-critical, defense, and energy applications are migrating to AI technology, FPGAs will be the only reliable solution able to provide high-speed data processing at high-level security. ENAS is a great combination of secure (TLS), fast, and reliable (TCP) communication.” said Andreas Schuler, Director Applications, MLE. “We’re helping some industry leaders in these fields to adopt ENAS to enable AI in their next-gen solutions.”
“We are excited about the secure FPGA-based connectivity solutions enabled by ENAS”, said Matti Tommiska, co-founder and CEO of Xiphera. “The increasing demands for both bandwidth and security will benefit from the joint solution developed in the partnership between MLE and Xiphera.”
Xiphera, Ltd, is a Finnish company designing hardware-based security solutions using standardised cryptographic algorithms. We have strong cryptographic expertise, extensive experience in system design, and deep knowledge on reprogrammable logic, enabling us to protect our customers’ critical information and assets.
Xiphera’s product portfolio consists of secure and efficient cryptographic Intellectual Property (IP) cores, designed directly for Field Programmable Gate Arrays (FPGAs) and Application Specific Integrated Circuits (ASICs). Our widely applicable solutions for various end markets offer our customers peace of mind in a dangerous world.
Contact information:
Mimmi Kuusisaari Marketing and Communications Coordinator marketing@xiphera.com
About MLE
Missing Link Electronics is a Silicon Valley-based technology company with offices in Germany. MLE is a partner of leading electronic device and solution providers and has been enabling key innovators in the automotive, industrial, test & measurement markets to build better Embedded Systems, faster. MLE’s mission is to develop and market technology solutions for Embedded Systems Realisation via pre-validated IP and expert application support, and to combine off-the-shelf FPGA devices with Open- Source Software for dependable, configurable Embedded System platforms. MLE’s expertise is Domain-Specific Architectures I/O connectivity and acceleration of data communication protocols, additionally opening up FPGA technology for analog applications, and the integration and optimisation of Open Source Linux and Android software stacks on modern extensible processing architectures.
Contact information
Andreas Schuler Director Applications andreas.schuler@missinglinkelectronics.com
