Modern Systems can combine a lot of sensors like cameras, radars, Lidar or high speed ADC/DAC. During development, it is often required to record raw data. A FPGA Based High Speed Recorder can collect data from many different sources and can record them on non-volatile memory. Building a High Speed Data Recorder has many pitfalls which can cause the project to fail as a single flaw can have a heavy impact on performance.
This presentation will walk through our lessons learned from building such a recorder: starting by analyzing the data path, discussing the impact of data granularity and data width, different local buffer options such as DDR / HBM2 / UltraRAM / BRAM, characteristics of AXI4 / PCIe and also the limitations of most NVMe SSDs in the aspect of sustained writing performance. Then the presentation will end with an architectural overview of the final system and the achieved performance.
Embedded systems such as in-vehicle networks, modern factory automation or autonomous robots, for example, are undergoing a major shift: Enabled by high-resolution cameras, Radar and Lidar sensors, AI algorithms can implement smartness and ambient awareness, but for this need more compute power and higher bandwidth. Industrial and automotive networks must now transport many Gigabits per second, while guaranteeing reliable and secure data delivery, on-time.
TCP, the Transmission Control Protocol, was introduced half a century ago and is a good protocol used almost everywhere in wired or wireless, robotics, factories, vehicles. Unfortunately, TCP has some bad aspects: A significant computational burden. And some outright ugly: Unpredictable tail latency and head-of-line blocking, making real-time behavior difficult.
Our presentation shares quantitative analysis results and presents alternatives: For latency analysis we present benchmarks results from network simulation which show the significant tail latencies for TCP and the undesirable outcomes of TCP’s “not-so-fair” scheduling.
As an alternative we present the Homa protocol from Stanford University. Instead of stream-based connections, Homa is message based and connectionless, which caters better to the needs of modern distributed, microserviced, virtualized embedded architectures. Homa provides significant advantages over TCP when it comes to tail latency and infrastructure efficiency in real-life networks.
With the new Encrypted Network Accelerator Solutions brought to the market, Xiphera and MLE offer a cryptographically secure and reliable connection between devices over TCP/IP.
Xiphera, Ltd, designing hardware-based security solutions using standardised cryptographic algorithms, and Missing Link Electronics (MLE) with expertise in offloading CPUs and accelerating software-rich system stacks via so-called Domain-Specific Architectures, announce a partnership to introduce Encrypted Network Accelerator Solutions (ENAS). With the joint solutions brought to the market, Xiphera and MLE offer a cryptographically secure and reliable connection between devices over TCP/IP.
The ENAS solutions combine MLE’s highly modular TCP/UDP/IP Network Protocol Accelerator Platform (NPAP) with Xiphera’s TLS 1.3 security protocol solution. While accelerating the device network up to 10/25/50 GigE, it implements Transport Layer Security (TLS), a cryptographic security protocol providing end-to-end data security, on top of the MLE’s Transmission Control Protocol (TCP) layer for more secure and accelerated network communication. The solution is delivered as an IP core for FPGA circuits.
The Encrypted Network Accelerator Solutions are best suited for applications where the highest security level and high-speed data transmission are required, such as critical communications in defense, space technology, and energy production and distribution. Since the TCP/IP stack and the TLS 1.3 security protocol – including importantly both key exchange and key management – are both executed entirely in hardware, the joint solution has both scalable high-speed performance and minimised attack surface, especially when compared to a software-based approach.
“As mission-critical, defense, and energy applications are migrating to AI technology, FPGAs will be the only reliable solution able to provide high-speed data processing at high-level security. ENAS is a great combination of secure (TLS), fast, and reliable (TCP) communication.” said Andreas Schuler, Director Applications, MLE. “We’re helping some industry leaders in these fields to adopt ENAS to enable AI in their next-gen solutions.”
“We are excited about the secure FPGA-based connectivity solutions enabled by ENAS”, said Matti Tommiska, co-founder and CEO of Xiphera. “The increasing demands for both bandwidth and security will benefit from the joint solution developed in the partnership between MLE and Xiphera.”
Xiphera, Ltd, is a Finnish company designing hardware-based security solutions using standardised cryptographic algorithms. We have strong cryptographic expertise, extensive experience in system design, and deep knowledge on reprogrammable logic, enabling us to protect our customers’ critical information and assets.
Xiphera’s product portfolio consists of secure and efficient cryptographic Intellectual Property (IP) cores, designed directly for Field Programmable Gate Arrays (FPGAs) and Application Specific Integrated Circuits (ASICs). Our widely applicable solutions for various end markets offer our customers peace of mind in a dangerous world.
Contact information:
Mimmi Kuusisaari Marketing and Communications Coordinator marketing@xiphera.com
About MLE
Missing Link Electronics is a Silicon Valley-based technology company with offices in Germany. MLE is a partner of leading electronic device and solution providers and has been enabling key innovators in the automotive, industrial, test & measurement markets to build better Embedded Systems, faster. MLE’s mission is to develop and market technology solutions for Embedded Systems Realisation via pre-validated IP and expert application support, and to combine off-the-shelf FPGA devices with Open- Source Software for dependable, configurable Embedded System platforms. MLE’s expertise is Domain-Specific Architectures I/O connectivity and acceleration of data communication protocols, additionally opening up FPGA technology for analog applications, and the integration and optimisation of Open Source Linux and Android software stacks on modern extensible processing architectures.
Contact information
Andreas Schuler Director Applications andreas.schuler@missinglinkelectronics.com
The AMD-Xilinx Security Working Grouptakes place face-to-face in Munich, Germany, from December 5-6, 2023. Presentations include the latest security features in Versal ACAP and updates for the product roadmap.
MLE, a Premier AMD Alliance Member, will participate and offer its security solutions and services. Solutions for ARM OP-TEE, TCP/IP with TLS (NPAP and TLS) in RTL for fast and secure communication and services for hardening AMD Zynq UltraScale+ MPSoC and AMD Versal based systems when used in datacenter networking and telecommunications.
AMD’s Kria KR260 Robotics Starter Kit builds on the success of AMD’s Kria System-on-Modules (SoM) and is an ideal platform to test ideas for multi-Gigabit networking. Because Kria KR260 integrates an AMD Zynq UltraScale+ MPSoC device, functions can be implemented using adaptive computing concepts: Either using the ARM A53 Quad-core CPUs and/or using programmable logic.
Missing Link Electronics (MLE) is an AMD Premier Adaptive Computing Partner. AMD’s Premier Agreements require that MLE maintains a high level of expertise and that MLE engineers complete AMD’s Certification and training requirements. Since 2012, MLE has been supporting AMD Zynq-7000 SoC and Zynq UltraScale+ MPSoC device projects with expertise in FPGA design and Linux Processing System software development.
Project Cross Collaboration at Robert BOSCH GmbH has been using the Kria KR260 Robotics Kit and has engaged with MLE for proving ideas for computer vision and IEEE 1722-style multi-Gigabit automotive networking. A demonstrator based on a Zone ECU and the Kria KR260 Robotics Kit has been presented at the IEEE SA Ethernet & IP Technology Day, September 2023 in Sao Paulo, Brazil.
Looking for FPGA-based Multi-Gigabit Automotive Networking Solution?
Says Prof. Dr.-Ing. Christian Waldschmidt, head of the institute:
Adding NVMe SSDs and MLE’s NVMe Streamer solved our need for high speed mass storage. As all came in the form of a reference design, it was easy to integrate in our system. The Standard AXI4 Stream interfaces allow an easy connection to our existing Digital Radar Design. The experts of Missing Link Electronics also helped with the development of a custom carrier board for the AMD Zynq Ultrascale+ RFSoC, NVMe and 100GbE interfaces.
NVMe (Non-Volatile Memory Express) has become the prominent choice for connecting Solid-State Drives (SSD) when storage read/write bandwidth is key. Electrically, the NVMe protocol operates on top of PCIe; it leaves behind legacy protocols such as AHCI, and thus scales well for performance. Licensing NVMe Streamer from MLE saved time and allowed us to focus on our research in Digital Radars.
Looking for FPGA-based NVMe SSD Acceleration Solution?
To address the acceleration needs of Disaggregated Computational Storage or At-Speed In-Network Processing, the featured solutions integrate MLE’s FPGA-based networking and storage accelerators with the latest ProDesign’s FALCON Agilex® 7 M Acceleration Card (based on Intel® Agilex® 7 FPGA), supporting up to 3x 400 GbE.
MLE and Trenz Electronic, both Premier Members of the AMD Adaptive Computing Partner Program, have collaborated and worked on Trenz’s new TE0950 AMD/Xilinx Versal™ AI Edge Evalboard to provide an integrated and pre-validated network and storage accelerating solution.
To realize network acceleration with AMD/Xilinx Versal™ AI Edge device, MLE implements the latest version of the TCP/IP Network Protocol Accelerator Platform which gains enhancements for performance and interoperability, on the TE0950 AMD/Xilinx Versal™ AI Edge Evalboard. Currently the 10G/25G TCP/IP Core is verified on the board in the Linux system, and testing with 50G/100G TCP/IP Core is also scheduled.
MLE also tested Opsero’s FPGA Drive FMC Gen4 with our NVMe Streamer, the full accelerator NVMe host subsystem, to enable high read/write bandwidth for SSD mass storage connectivity. We implement and verify a single PCIe x4 Gen4 SSD with 16GT/s transfer rate on the TE0950 AMD/Xilinx Versal™ AI Edge Evalboard.
MLE is dedicated to de-risking system design via integration and development services and FPGA Full System Stacks. Through testing in the MLE lab, we can verify the compatibility between Trenz’s new TE0950 board and our IP-core accelerators and its performance in accelerating networking and storage.
The Storage Developers Conference (SDC) 2023 of SNIA, the Storage and Networking Industry Alliance, will be held Sept. 18-21 in Fremont, CA.
There, MLE will present “How Bad is TCP? (And What Are the Alternatives?)“. TCP is ubiquitous, however, it has some significant drawbacks including unpredictable tail latency and a significant computational burden. MLE will share quantitative analysis results and describing alternatives.
One of which is the “Homa” protocol from John Ousterhout’s team at Stanford University. Homa is an implementation of a so-called Quad-RP, i.e. Rapid, Reliable Request-Response Protocol: Instead of streams it is message based and connectionless, which caters better to the needs of modern distributed, microserviced, virtualized architectures.