From Tuesday to Thursday, February 25-27, 2020, MLE will exhibit at Embedded World Conference 2020 in Nuremberg, Germany. For expert discussions on FPGA-based architectures for automotive, industrial and other embedded systems please visit MLE in Hall 3A Booth 331.
With great support from the Intel PSG Team Europe, MLE has ported the 10/25 Gigabit Ethernet Network Protocol Acceleration Platform (NPAP) based on the TCP/UDP/IP Network Protocol Accelerator from Fraunhofer Heinrich-Hertz-Institute Berlin, Germany, to Intel’s Stratix 10 Device Family. This lays the necessary foundation to perform TCP/UDP/IP protocol full acceleration for users of Intel’s new Stratix 10 based FPGA Programmable Accelerator Cards (PAC) D-5005.
Following a successful review by the Xilinx Security Center-of-Excellence, MLE now releases the OP-TEE Free Open-Source Edition for the Zynq UltraScale+ MPSoC and RFSoC devices from Xilinx (ZynqMP). OP-TEE is an open-source project under the Linaro Security Working Group (SWG) for the ARM Trusted Execution Environment (TEE). Team MLE volunteered and took responsibility for maintaining functions specific to ZynqMP. Read more information on MLE’s offerings for Security and Trust. OP-TEE can be downloaded at www.github.com/OP-TEE/
The automated Vivado Build System, open-sourced by MLE to increase FPGA design productivity, is featured in the Xilinx Blog. This collection of scripts facilitates Continuous Integration (CI), and ensures fully reproducible results later in the development and product lifecycle.
MLE releases NVMe Streamer which is a so-called Full Accelerator NVMe host subsystem integrated into FPGAs. NVMe Streamer offloads the NVMe protocol into programmable logic and enables to stream data from FPGA blocks in and out of directly-attached NVMe SSDs.
Missing Link Electronics has been awarded another patent in the field of mixed-signal: US Patent 10,509,880 B2 was issued DEC 17 2019 and claims novel Electronic Design Automation (EDA) methods for Sigma-Delta Modulation in FPGA-based Mixed-Signal Systems enabling Analog FPGA I/O.
To facilitate an FPGA Build Environment which can be automated, for example for Continuous Integration (CI), and which ensures fully reproducible results later in the development and product lifecycle, the Team at Missing Link Electronics has put together a collection of scripts. Currently focused on the Xilinx Vivado toolchain (Version 2016.4 or newer) and tested under Ubuntu Linux 16.04 LTS and 18.04 LTS, this scripted FPGA Build Environment has recently been made available at GitHub (https://github.com/missinglinkelectronics/vivado-build-system ) under open source Apache 2.0 license.
Team MLE welcomes any feedback and contribution from the FPGA ecosystem!
November 12-13, 2019, Missing Link Electronics, a Xilinx Alveo Independent Software Vendor (ISV), exhibits at the Xilinx Developers Forum Europe (XDF). Alveo Accelerators for Key-Value-Store (KVS), Data-in-Motion labelling, compression and encryption facilitate ADAS / Autonomous Vehicle AI-in-the-Loop testing at speeds of 100 Gbps. Please stop by and visit us.
October 1-2, 2019, Missing Link Electronics is a Silver Sponsor of the Xilinx Developers Forum (XDF) in San Jose, CA, where we will be presenting solutions for FPGA Acceleration and for Security / ARM Trusted Execution Environment (OP-TEE). Please stop by and visit us at Booth 35.