Company - Missing Link Electronics

MLE Awarded AMD 2023 Premier Adaptive Computing Partner of the Year

June 28, 2024Alveo, AMD, High Speed Data Recording

MLE wins AMD 2023 Premier Adaptive Computing Partner — AMD’s Donna Best (left) and Rhett Whatcott (right) awarded MLE’s Bob Baker (middle) the AMD 2023 Premier Adaptive Computing Partner of the Year award.

San Jose, CA, June 2024 – At the AMD Premier Partner and ATP Summit 2024 held in San Jose this June, Missing Link Electronics (MLE) was honored with the Premier Adaptive Computing Partner of the Year award for the EMEA region. This recognition highlights MLE’s outstanding contributions and unwavering commitment to advancing AMD FPGA technology across various industries and applications.

Since becoming a member of the AMD Partner Program in 2011, MLE has played an essential role in driving the adoption and integration of AMD’s cutting-edge FPGA technology. MLE has leveraged its expertise to promote AMD’s Alveo technology, particularly the Alveo U55 and Alveo V80, through its involvement in key customer engagements for data recording for high-speed cameras.

MLE wins AMD Premier Adaptive Computing Partner Award 2023

MLE’s deep understanding of FPGA computing has allowed it to position AMD’s Alveo technology as a cornerstone for high-performance applications. The company’s strategic initiatives and technical acumen have made Alveo technology more accessible and attractive to more customers, thereby enhancing its adoption and integration into various sophisticated systems.

AMD recognizes MLE’s current contributions to the Alveo U55 and V80 as a catalyst for future engagements, broadening the customer base and enhancing the technology’s growth potential.

In their nomination statement, AMD highlighted:

Missing Link Electronics’ dedication to promoting innovative technologies across various applications continues to be vital, and their valuable contributions to the field make them deserving of recognition and this award.

This accolade from AMD not only acknowledges MLE’s past achievements but also underscores the potential for future collaborations and innovations. As the demand for high speed networking and storage grows, MLE is well-positioned to continue its leadership in the field, driving further advancements and expanding the reach of AMD’s technology.

MLE’s commitment to excellence is reflected in its ongoing projects and future plans. We are constantly exploring new FPGA technologies to ensure users to efficiently adopt AMD FPGAs. Our ability to adapt and meet changing market needs has made it a valued partner of AMD and a key player in the technology space.

Berlin 6G Conference 2024

June 28, 20246G, Precision Time Protocol (PTP), White Rabbit

Berlin 6G Conference is the annual networking event of the German 6G Program, organized by the 6G Platform Germany, will take place at the Berlin Congress Center (BCC) from July 2-4, 2024.

The 6G Platform Germany is an R&D initiative with a total funding of €700 million. One of the core topics is the combination of a secure radio and sensing, so-called Integrated Communication and Sensing (ICAS) with aims to develop such a combination for communication and sensing of the environment and to integrate it into a joint system for the future mobile radio standard 6G.

MLE has been actively contributing to the 6G-ICAS4Mobility project in respect of high-accuracy networking technology with precision time synchronization.

MLE Presents “FPGA Based 400GBit/s Data Recorder – Insight into Different Pitfalls and Design Choices” at FPGA Conference 2024

June 18, 2024BRAM, High Bandwidth Memory (HBM2), High Speed Data Recording, NVMe SSD, PCI Express, Storage Acceleration

FPGA Conference EW24 Banner - 400Gbit FPGA Data Recording IP

The FPGA Conference Europe 2024 will be held July 2-4 in Munich, Germany. There, MLE will present “FPGA Based 400GBit/s Data Recorder – Insight into Different Pitfalls and Design Choices.”

Modern Systems can combine a lot of sensors like cameras, radars, Lidar or high speed ADC/DAC. During development, it is often required to record raw data. A FPGA Based High Speed Recorder can collect data from many different sources and can record them on non-volatile memory. Building a High Speed Data Recorder has many pitfalls which can cause the project to fail as a single flaw can have a heavy impact on performance.

This presentation will walk through our lessons learned from building such a recorder: starting by analyzing the data path, discussing the impact of data granularity and data width, different local buffer options such as DDR / HBM2 / UltraRAM / BRAM, characteristics of AXI4 / PCIe and also the limitations of most NVMe SSDs in the aspect of sustained writing performance. Then the presentation will end with an architectural overview of the final system and the achieved performance.

Date: Tuesday July 2th, 2024

Track 1 – Application (starts at 4:30pm CEST)

Location: Hotel NH München Ost Conference Center, Munich, Germany

Join us at FPGA Conference 2024 to learn more details about the high-speed 400GBit/s data recording technology!

MLE Presents “Light Rabbit: Implementing a White Rabbit node on COTS AMD development boards without relying on external VCXOs” at The 13th White Rabbit Workshop

March 22, 2024AMD ZC706, AMD ZCU102, FPGA, Mixed-Mode Clock Managers, MMCMs, QPLL, Quad Phase-Locked-Loops, White Rabbit

The 13th White Rabbit Workshop will be held March 21-22 at CERN in Geneva, Switzerland. There, MLE will present “Light Rabbit: Implementing a White Rabbit node on COTS AMD development boards without relying on external VCXOs.”

White Rabbit is a technology that allows to synchronize networked devices or endpoints tens of kilometers apart with a sub-nanosecond accuracy. With minor, but incompatible changes, it is now fully integrated into the IEEE1588-2019 or PTP v2.1 standard as high accuracy (HA) profile.

Each endpoint employs frequency and phase measurement and adjustment techniques using field programmable gate arrays (FPGAs) and external voltage-controlled crystal oscillators (VCXOs). This usually requires external circuit boards with specific components not available on commercially off-the-shelf (COTS) development boards.

At the workshop, we will share our results of implementing White Rabbit nodes on multiple development boards, e.g. AMD ZC706 and ZCU102 by only using the FPGA’s resources such as either Mixed-Mode Clock Managers (MMCMs) on the ZC706 or Quad Phase-Locked-Loops (QPLL) on the ZCU102, capable of fully synchronizing with other White Rabbit hardware, such as a Seven Solutions White Rabbit switch (WRS 3/18).

We also compared our synchronized endpoints on the ZCU102 and ZC706 to the timing source of the White Rabbit switch. We obtained initial experimental results of our two VCXO-less White Rabbit implementations using a time interval counter (TIC) for measuring the generated pulse-per-second (PPS) signal and a custom Digital Dual Mixer Time Difference (D-DMTD) circuit for the 10 MHz signal. To validate our measurement approach, we also did a spectrum analysis and a time-interval error analysis of the 10 MHz signals with a professional Rohde&Schwarz RTO1044 oscilloscope.

Date: Thursday March 21, 2024

Session 1.9: 1:30pm-1:55pm CEST

Location: CERN in Geneva, Switzerland

MLE Updates TCP/UDP/IP Network Protocol Accelerator Platform

March 18, 2024AMD Versal, IP Update, Network Acceleration, NPAP, TCP/IP

MLE has released an update, Version 2.3.3., of its Network Protocol Acceleration Platform (NPAP).

This update is fixing minor issues with AXI4 bus scheduler fairness, IP Core packaging for AMD/Xilinx Versal FPGA as well as UDP only instantiations. All licensees who are on an active maintenance contract with MLE will have access to this update.

We suggest that customers who are in a late phase of an FPGA design project integrating MLE NPAP shall contact MLE to discuss risks and benefits when updating.

Visit http://MLEcorp.com/NPAP for more information.

Shift-Left Your FPGA Design Project with FPGA Full System Stacks from Trenz Electronic and MLE

March 7, 2024AMD Versal, High Speed Data Recording, High Speed Data Streaming, Intel Agilex 5, Network Acceleration, Robo/TSN, TCP/IP, trenz

Visit us at Embedded World 2024!

The Embedded World 2024 tradeshow will be held April 9-11 in Nuremberg, Germany. Here, partners Trenz Electronic and MLE will present solutions for you to “shift-left” your FPGA design projects. These are FPGA Full System Stacks comprising off-the-shelf FPGA System-on-Modules (SoM) from Trenz Electronic plus FPGA subsystems and IP cores from MLE.

Our FPGA Full System Stacks have a particular focus on high-speed connectivity using PCI Express, MIPI CSI-2, GMSL, Multi-Gigabit Ethernet. We target applications which require reliable, low-latency, high-throughput network transports, high-speed data acquisition, augmented stereo computer vision, high-speed data record & replay. All those are driven by AI algorithms processing massive data from high-resolution cameras, Radar and Lidar sensors.

Please visit us to experience the featured solutions built on top of the latest Trenz SoMs:

TEI0187 based on Altera’s Agilex^® 5 FPGA

TE0950 based on AMD Versal™ AI Edge FPGA

We also invite you to join the Embedded World Conference where our engineers present FPGA technology for embedded networking acceleration for high-speed data streaming:

TCP/IP for Real-Time Embedded Systems: The Good, the Bad and the Ugly

Session 2.5: starts 1:45pm CEST

April 9th, 2024 (Tue)

FPGA Based High Speed Recording – Do’s and Don’t’s of Building a 400GBit/s Data Recorder

Session 8.2: starts at 1:45pm CEST

April 10th, 2024 (Wed)

Architecture and Performance of Integrated High-speed and Versatile Embedded Networking

Session 1.9: starts 2:30pm CEST

April 11th, 2024 (Thu)

Trade Show Information

Date: April 9-11, 2024

Location: Nuremberg Convention Center, Nuremberg, Germany

Booth: Hall 5 #112

Visit us at booth #5-112 and talk with our FPGA experts to learn about how to shift-left your FPGA design projects with FPGA Full System Stacks!

Yi-Ying Li (Sandy)

Director Technology Solutions

yiying.li@missinglinkelectronics.com

MLE Presents “Architecture and Performance of Integrated High-speed and Versatile Embedded Networking” at Embedded World 2024

March 5, 2024High Speed Data Streaming, Network Acceleration, Precision Time Protocol (PTP), ZYNQ Ultrascale+

The Embedded World Conference 2024 will be held April 9-11 in Nuremberg, Germany. There, MLE will present “Architecture and Performance of Integrated High-speed and Versatile Embedded Networking.”

These days high-performance embedded systems operate highly interconnected. Within these networks the systems often transport data at high bandwidth or low-latency. While the system needs to serve the network performance needs, additional control tasks are to be performed. For the latter task usually a processing system runs a Linux or another real-time embedded operating system. Then the former, high-performance network data cannot be fully handled by the embedded processing system.

To overcome this situation, a network stack implemented in hardware, e.g. in an FPGA, can offload the processing subsystem. To simplify the system design and reduce cost, the number of physical networking interfaces can be reduced to one. This, on the other hand, requires an architecture that shares a single high-speed network interface across the processing system and the hardware network stack. Usually, embedded systems in addition require highly accurate time synchronization, usually provided via PTPv2.

The presentation shares the architecture options and results based on an implementation for a high-speed streaming data interface, both a source and a sink that shares a physical network interface with a open source network interface card implementation connected to a processing system. This NIC is operated by a Linux driver and allows for PTPv2 based time synchronization via a Linux daemon. The whole system is implemented into an AMD MPSoC.

Date: Thursday April 11th, 2024

Session 1.9 Internet of Things / Platform 2 (starts 2:30pm CEST)

Location: NCC Ost Convention Center, Nuremberg, Germany

Join us at EW24 Conference to learn about the latest time synchronization technology for high-speed data streaming!

MLE Presents “FPGA Based High Speed Recording – Do’s and Don’t’s of Building a 400GBit/s Data Recorder” at Embedded World 2024

March 5, 2024BRAM, High Bandwidth Memory (HBM2), High Speed Data Recording, NVMe SSD, PCI Express, Storage Acceleration

The Embedded World Conference 2024 will be held April 9-11 in Nuremberg, Germany. There, MLE will present “FPGA Based High Speed Recording – Do’s and Don’t’s of Building a 400GBit/s Data Recorder.”

Date: Wednesday April 10th, 2024

Session 8.2 System-on-Chip (SoC) Design / FPGA Design (starts at 1:45pm CEST)

Location: NCC Ost Convention Center, Nuremberg, Germany

Join us at EW24 Conference to learn about the latest high-speed data recording technology!

MLE Presents “TCP/IP for Real-Time Embedded Systems: The Good, the Bad and the Ugly” at Embedded World 2024

March 5, 2024Homa, Network Acceleration, TCP/IP

The Embedded World Conference 2024 will be held April 9-11 in Nuremberg, Germany. There, MLE will present “TCP/IP for Real-Time Embedded Systems: The Good, the Bad and the Ugly.”

Embedded systems such as in-vehicle networks, modern factory automation or autonomous robots, for example, are undergoing a major shift: Enabled by high-resolution cameras, Radar and Lidar sensors, AI algorithms can implement smartness and ambient awareness, but for this need more compute power and higher bandwidth. Industrial and automotive networks must now transport many Gigabits per second, while guaranteeing reliable and secure data delivery, on-time.

TCP, the Transmission Control Protocol, was introduced half a century ago and is a good protocol used almost everywhere in wired or wireless, robotics, factories, vehicles. Unfortunately, TCP has some bad aspects: A significant computational burden. And some outright ugly: Unpredictable tail latency and head-of-line blocking, making real-time behavior difficult.

Our presentation shares quantitative analysis results and presents alternatives: For latency analysis we present benchmarks results from network simulation which show the significant tail latencies for TCP and the undesirable outcomes of TCP’s “not-so-fair” scheduling.

As an alternative we present the Homa protocol from Stanford University. Instead of stream-based connections, Homa is message based and connectionless, which caters better to the needs of modern distributed, microserviced, virtualized embedded architectures. Homa provides significant advantages over TCP when it comes to tail latency and infrastructure efficiency in real-life networks.

Date: Tuesday April 9th, 2024

Session 2.5 Connectivity Solutions / Application Layer Protocols (starts 1:45pm CEST)

Location: NCC Ost Convention Center, Nuremberg, Germany

Join us at EW24 Conference to learn about the latest TCP/IP technology for high performance computing!